Example questions Flashcards
What does HDL stand for?
Hardware description language
What is a Field Programmable Gate Array?
This is an array of logic gates that can be manipulated to run a logical program.
What does FPGA stand for?
Field Programmable Gate Array.
The core component of an FPGA?
Configurable logic block.
The four main components within the CLB?
and multiplexer
What is the meaning of the term primitives in system Verilog?
All logic libraries have or can easily implement basic logic functions.
SystemVerilog implements a predefined set of logic functions, called primitives, that can be used instead of the library cells:
and(), nand(), or(), nor(), xor(), xnor(), not()
The output is always the first wire in the list
There can be as many inputs as required
Example: and U1(outputSignal, inputSignal1, inputSignal2); This makes designs more “portable” between technologies.
What is the meaning of instantiation in SystemVerilog?
The are two types of instantiation commonly used:
Instantiation with positional port mapping:
Signals are connected to the instanciated lower level module in the same order as they were defined in the low-level module
FullAdder bit1(A1,B1,C1,S1,C2)
]Not good as it is easy for this to be incorrect
Instantiation with positional port mapping
The names of the ports of the lower-level subsystem are provided with the signals
they are being connected to.
FullAdder bit1 (.A(A1),.B(B1),.C(C1),.Sum(S1),.Carry(C2)); The port connections can be listed in any order
What is the meaning of hierarchy in system verilog?
SystemVerilog allows us to include lower-level subsystems within a higher-level module to achieve the desired functionality.
This design approach, called hierarchy, is a good design practice that enables design partitioning.
Implement the circuit
What are the four values that the logic data type can take?
1,0,X,Z
Suppose you have the following vectors in system Verilog?
input logic [5:0]A;
output logic [5:0]B;
//supose A = 010101
Set output B with the value of A shifted to the left by three positions.
assign B << 3
Implement the digital system shown in the schetamtic below
assign F = (sel == 1) ? (B&C) : (A&C);
Explain the function of the operator ‘≫’, using and example in SystemVerilog
This operator is used for shiting.
Give and example
a << 3
shifts a three to the left
Give an example of continuous assignment using ‘assign’ in SystemVerilog
assign A = B+C;
What are the benefits of ‘enum’ and ‘struct’ data types, and give an example of each data type using SystemVerilog code.
Struct can have different data types while enum, have to be all the same length and data type.
Explain the use and benefit of parameter in the description and instantiation of a module?
Parameters can be used to scale a design
- The list #(parameter name=value …) is added into the module definition before the ports.
- The named parameters are used in for-loops etc. to scale the design.
- The default parameter value can be over-ridden in the instantiation.
Explain the use of blocking (=) and non-blocking (<=) assignments using always_comb and always_ff blocks in SystemVerilog.
Blocking executes code in sequence, as the code is blocked together.
Non-blocking means that the code is executed in parrallel at the same time.
always_comb
Describe the following diagram using two different approaches:
a. ‘if-else’ and a combinatorial block
b. ‘case’ and a combinatorial block
if sel = 1
out = in1
else
out = in0
always_comb
begin
case(Sel)
1: Out=in1;
2: Out=in0;
default
endcase
end
Design a 4-bit Counter module using SystemVerilog. The counter should increment by 1 with the positive edge of the clock. The counter should set to 0 with the positive edge of the reset. Write down the complete SystemVerilog code.
module Counter()
(
input logic Clock,
input logic Reset,
output logic [3:0] Count
);
always_ff @(posedge Clock, posedge Reset)
begin
if(Reset)
Count <= ‘0;
else
Count = Count + 1
end
endmodule
Design a N-bit Counter module using SystemVerilog. The counter should increment by 1 with the positive edge of the clock. The counter should set to 0 with the positive edge of the reset. Write down the complete SystemVerilog code.
N=4
module Counter()
(
input Reset
output [N-1:0] Count
);
begin
if(Reset)
assign Count <= ‘0;
elseif(Count <= 2^(N))
assign Count <= ‘0;
else
assign Count = Count + 1
end
endmodule
Write the complete SystemVerilog code of a 4-bit ring counter. Use the following truth table as a guide.
module RingCounter
(
input logic Clock,
input logic Reset,
output logic [3:0] Count
);
always_ff @(posedge Clock, posedge Reset)
begin
if(Reset) Count <= 0’d1;
else Count <= {Count[2:0], Count[3]};
end
endmodule
Describe using diagrams and text the architecture of the Ripple Carry Adder and Carry Lookahead Adder. Give an advantage and disadvantage of each adder.
A 4 bit ripple counter shown here, contains 4 Full adders, here the carry from each adder is fed into the next significant bit.
The advantage of this adder is that this a simple design that is cheap to construct and an easy to understand
An advantage of the ripple counter is that the more bits are added (example 32 bits) the slower the adder will get as the carry has to ripple down the line.
The Carry lookahead adder, contains circuitry that is represented by the C blocks in the diagram that is able to predict the carry status fro the forth comining adder. This operates by defining carry generate and carry propagation
- Carry is generated if the adder produces a carry out independent of the carry in. A carry Ci is guaranteed if Ai and Bi are both 1 (Gi=Ai Bi).
- Carry is generated if the adder produces a carry out whenever there is a carry in. A carry will be propagated if either Ai or Bi is 1.
An advantage to this design is that the adder can be extended indefinitely without the speed of the device is considerably affected.
Disadvantage, additional circuitry is required to operate the lookahead function.
What is the decimal representation of the unsigned number 1101.101 ?
13.675
What is the binary representation using two’s complement of -2.375?
1101.1010
