2 Gate Level, Hierarchy and Simulation

Question 1

Why were CAD packages required?

Answer 1

Digital systems involved hundreds or thousands of circuits, which increase their complexity in design. Therefore, computer-aided design (CAD) tools were introduced for the hardware design process.

Question 2

What is schematic capture?

Answer 2

This is used to describe the circuits and wiring to there input and output ports.

Question 3

HDL?

Answer 3

Hardware description language

Question 4

Why do we need a HDL?

Answer 4

Building very large logic circuits (>~100k gates) is almost impossible with schematic based design. Hardware description languages (HDL) such as SystemVerilog provide the next level for hardware designers.

Question 5

System Verilog relevance?

Answer 5

This HDL is widely accepted in the digital design industry and has become a must know for design engineers and students in electronics and computing fields.

Question 6

Why system Verilog x3?

Answer 6

• SystemVerilog is a Hardware Description Language (HDL). Resembles a software programming language but it has features not present in programming languages.
• SystemVerilog allows us to write a textual description of a digital design
• The hardware of a computer can be described using SystemVerilog.

Question 7

How does SystemVerilog allow us to write a textual description of a digital design

Answer 7

• Can be synthesised into the circuit by automated tools
• Can be tested in a simulator to remove bugs
• Can be reused in larger designs

Question 8

The hardware of a computer can be described using SystemVerilog. SystemVerilog is:

Answer 8

• Industrially relevant and widely accepted by design engineers
• Hierarchical description of hardware
• Reusable

Question 9

Gate Level design?

Answer 9

Creating a hardware design that maps directly to the target technology is “gate-level” design

Question 10

In gate level design what is done?

Answer 10

• Each gate is described
• Each connection is described
• There can be hierarchy in the design

Question 11

EXample of Gate level design?

Answer 11

Question 12

The process of creating a digital system designed with gate-level SystemVerilog can be automated by tools performing:

Answer 12

• Place and route
• Verification
• Fabrication
  *

Question 13

Place and Route

Answer 13

Arrangement of components and wire all connections to minimise the area needed and interconnect length and crossing

Question 14

Verification

Answer 14

The gate and wiring delays are used to estimate whether the final design meets the requirements from the specification.

Question 15

Fabrication

Answer 15

The design is implemented in the FPGA.

Question 16

Primitives

Answer 16

All logic libraries have or can easily implement basic logic functions

System Verilog implements a predefined set of logic functions, called primitives, that can be used instead of the library cells.

such as and(), nand(), or()

Question 17

The advantages of primitives?

Answer 17

This makes designs more “portable” between technologies.

Question 18

Primitives in code?

Answer 18

Question 19

Hierarchy?

Answer 19

Hierachy can be implemented into system Verilog which allows us to include lower-level subsystems within a higher-level module to chive the desired functionality. This is a good design practice that enables design partitioning.

Question 20

Instantiation with positional port mapping

Answer 20

Signals are connected to the instantiated low-level module in the same order as they were defined in the low-level module.

FullAdder bit1 (A1,B1,C1,S1,C2);

Positional port mapping is prone to misconnections due to mistakes in the signal order.

Question 21

Instantiation with explicit port mapping

Answer 21

The names of the ports of the lower-level subsystem are provided with the signals they are being connected to.

FullAdder bit1 (.A(A1),.B(B1),.C(C1),.Sum(S1),.Carry(C2));

The port connections can be listed in any order.

FullAdder bit1 (.A(A1),.B(B1),.Sum(S1),.Carry(C2),.C(C1));

Question 22

If all the signals outside the module have the same name as the signals inside the module, the port names can be omitted too:

Answer 22

FullAdder bit_lucky (.*);

Question 23

If the signals outside the module have the same name as the signals inside the module, the wire name can be omitted:

Answer 23

FullAdder bit3 (.A(A3),.B(B3),.C(C3),.Sum(S3),.Carry);

Question 24

Simulation tools provide two major approaches:

Answer 24

• Graphical output

Useful for fault finding

• Text output

Useful for repetitive testing

Question 25

what is used to test a system?

Answer 25

In SystemVerilog we can use a testbench to test a system. This mechanism generate input patterns to drive the system and observe the outputs to verify the correct operation.

Question 26

What is a test bench?

Answer 26

• A testbench is an HDL description with a set of input conditions, patterns and sequence of operations.
• A testbench has no inputs and outputs
• A testbench can be composed of a number of files and modules

Question 27

unit under test

Answer 27

The testbech allows us to test a “unit under test” (UUT) or “device under test” (DUT). The outputs from the UUT are used to verify the functionality of the design.

Question 28

Example testbench

Answer 28