2 Gate Level, Hierarchy and Simulation Flashcards
Why were CAD packages required?
Digital systems involved hundreds or thousands of circuits, which increase their complexity in design. Therefore, computer-aided design (CAD) tools were introduced for the hardware design process.
What is schematic capture?
This is used to describe the circuits and wiring to there input and output ports.
HDL?
Hardware description language
Why do we need a HDL?
Building very large logic circuits (>~100k gates) is almost impossible with schematic based design. Hardware description languages (HDL) such as SystemVerilog provide the next level for hardware designers.
System Verilog relevance?
This HDL is widely accepted in the digital design industry and has become a must know for design engineers and students in electronics and computing fields.
Why system Verilog x3?
- SystemVerilog is a Hardware Description Language (HDL). Resembles a software programming language but it has features not present in programming languages.
- SystemVerilog allows us to write a textual description of a digital design
- The hardware of a computer can be described using SystemVerilog.
How does SystemVerilog allow us to write a textual description of a digital design
- Can be synthesised into the circuit by automated tools
- Can be tested in a simulator to remove bugs
- Can be reused in larger designs
The hardware of a computer can be described using SystemVerilog. SystemVerilog is:
- Industrially relevant and widely accepted by design engineers
- Hierarchical description of hardware
- Reusable
Gate Level design?
Creating a hardware design that maps directly to the target technology is “gate-level” design
In gate level design what is done?
- Each gate is described
- Each connection is described
- There can be hierarchy in the design
EXample of Gate level design?
The process of creating a digital system designed with gate-level SystemVerilog can be automated by tools performing:
- Place and route
- Verification
- Fabrication
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Place and Route
Arrangement of components and wire all connections to minimise the area needed and interconnect length and crossing
Verification
The gate and wiring delays are used to estimate whether the final design meets the requirements from the specification.
Fabrication
The design is implemented in the FPGA.
Primitives
All logic libraries have or can easily implement basic logic functions
System Verilog implements a predefined set of logic functions, called primitives, that can be used instead of the library cells.
such as and(), nand(), or()
The advantages of primitives?
This makes designs more “portable” between technologies.
Primitives in code?
Hierarchy?
Hierachy can be implemented into system Verilog which allows us to include lower-level subsystems within a higher-level module to chive the desired functionality. This is a good design practice that enables design partitioning.
Instantiation with positional port mapping
Signals are connected to the instantiated low-level module in the same order as they were defined in the low-level module.
FullAdder bit1 (A1,B1,C1,S1,C2);
Positional port mapping is prone to misconnections due to mistakes in the signal order.
Instantiation with explicit port mapping
The names of the ports of the lower-level subsystem are provided with the signals they are being connected to.
FullAdder bit1 (.A(A1),.B(B1),.C(C1),.Sum(S1),.Carry(C2));
The port connections can be listed in any order.
FullAdder bit1 (.A(A1),.B(B1),.Sum(S1),.Carry(C2),.C(C1));
If all the signals outside the module have the same name as the signals inside the module, the port names can be omitted too:
FullAdder bit_lucky (.*);
If the signals outside the module have the same name as the signals inside the module, the wire name can be omitted:
FullAdder bit3 (.A(A3),.B(B3),.C(C3),.Sum(S3),.Carry);
Simulation tools provide two major approaches:
- Graphical output
Useful for fault finding
- Text output
Useful for repetitive testing
what is used to test a system?
In SystemVerilog we can use a testbench to test a system. This mechanism generate input patterns to drive the system and observe the outputs to verify the correct operation.
What is a test bench?
- A testbench is an HDL description with a set of input conditions, patterns and sequence of operations.
- A testbench has no inputs and outputs
- A testbench can be composed of a number of files and modules
unit under test
The testbech allows us to test a “unit under test” (UUT) or “device under test” (DUT). The outputs from the UUT are used to verify the functionality of the design.
Example testbench
