12 MIPS and High RISC microprocessors Flashcards
A RISC (Reduced Instruction Set Computer) architecture employs:
small number of instructions (nowadays, this is not 100% accurate)
- simple instructions that execute quickly
- larger number of registers
- operations are performed between registers
RISC philosophy
RISC philosophy is about the use of elementary/lowlevelcomplexity instructions that execute quickly!
The MIPS microprocessor is an example of a RISC architecture.
details
- developed in the 1980s at Stanford University
- implements a small and simple ISA
- allows the implementation of pipelining
- uses 32 general purpose registers of 32 bits width
The MIPS microprocessor, which now belongs to MIPS Technologies Inc., has been successful and widely used in:
embedded systems
Nintendo and Sony products
Cisco Internet routers and switches
MIPS register structure diagram?
MIPS To refer to registers we can use the following notation:
- R0, R1, …, R31 or
- $0, $1, …, $31
MIPS Some special registers are:
- R0 has a value of zero
- R29 to R31 are use for subroutines or function calls
MIPS Other register that are not part of the register file:
Program Counter (PC)
MIPS Register addressing By convention we use:
$t:<register> indicates temporary result ($t5)</register>
$s:<register> indicates operation result ($s7)</register>
MIPS microprocessor, overview of specific and struct values for the general purpose registers.
MIPS microprocessor does not enforce a specific and strict use for the general purpose register, except for register R0. Nowadays, there is a convention for the use of registers and this is employed by compilers and simulators.
MIPS uses the following format for instructions
MIPS register positions?
R-type instructions
I-Type Instructions?
Sign extension MIPS
J-type instructions
What makes MIPS a load/store register file approach?
Issues with MIPS memory?
MIPS memory types
MIPS microprocessor datapath
MIPS program counter
MIPS Instruction memory and data memory:
MIPS Registers:
MIPS ALU?
Example of datapath for instruction: add R1, R2, R3 R-type instruction, uses 3 registers, 2 source registers and 1 destination register
MIPS implements the fetch-execute cycle with 5 stages
HighRISC layout
The microprocessor that you are developing has a reduced and simple set of instructions. We call it HighRISC microprocessor
HighRISC Instruction set?
