3 The Module data types and operators

Question 1

System Verilog Module?

Answer 1

A SystemVerilog design describes the hardware module of a system. This design, which will carry out some function, will eventually be synthesised into hardware.

The main component of a SystemVerilog design is the module which includes the interface to the system and description of the behaviour.

Question 2

Module diagram with inputs and outputs?

Answer 2

Question 3

System verilog internal module structure?

Answer 3

Question 4

Example of a logic gate AND with 2 input bits.

Answer 4

Question 5

SystemVerilog supports four basic values that a signal can take on:

Answer 5

SystemVerilog supports four basic values that a signal can take on: 0, 1, X and Z. The data types in SystemVerilog store these values.

Question 6

Net Data types?

Answer 6

Net data types model the interconnection between components and can take values 0, 1, X and Z. The most common net data type is the wire.

Question 7

Variable data types?

Answer 7

SystemVerilog contains many types that model storage which are called variable data types. These data types hold the value assigned to them until their next assignment.

Question 8

The most important variable data type?

Answer 8

The most important variable data type is logic, which is 4-valued and allows to represent values 0, 1, X, Z, and is useful to create warnings in simulations if a value is not set.

Question 9

What are busses?

Answer 9

• It is often necessary to handle multi-bit values (busses).
• SystemVerilog allows to create busses or vectors, which are one-dimensional array of elements.
• Net data types and variable data types can be used to create busses.

Question 10

Syntax required to create busses or vectors?

Answer 10

Question 11

wire [7:0] Sum;

Answer 11

// 8-bit vector called ‘Sum’ of type wire. MSB

// has the index 7 and LSB has the index 0.

Question 12

logic [15:0] Q;

Answer 12

// 16-bit vector called ‘Q’ of type logic.

Question 13

logic [11:0] address;

Answer 13

// This defines a 12-bit vector called ‘address’

// of type logic.

Question 14

How can individual bits within the vector be addressed?

Answer 14

Individual bits within the vector can be addressed using their index.

address[0]; // This is the least significant bit of the vector ‘address’

address[11]; // This is the most significant bit of the vector ‘address’

address[6]; // This the 7th bit of the vector ‘address’

Question 15

How can groups of bits be addressed?

Answer 15

Using an index range

address[3:0]; // This is the lower 4 bits of the vector ‘address’

address[11:8]; // This is the upper 4 bits of the vector ‘address’

Question 16

What are arrays?

Answer 16

SystemVerilog also allows to create multidimensional arrays of elements, which can be seen as a “vector of vectors”. Vectors within the array all have the same dimensions.

Question 17

Syntax required for array configuration?

Answer 17

Question 18

Logic [7:0] Mem [0:9];

Answer 18

// Defines an array of 10 vectors of type logic,

// where each vector is composed of 8 bits

Question 19

Integer A [0:99];

Answer 19

// Defines an array of 100 integers

Question 20

Mem Map?

logic [7:0] Mem [0:9];

Answer 20

Question 21

Numbers in SystemVerilog use the following syntax:

Answer 21

<size_in_bits>'<base></base>
<value></value></size_in_bits>

Question 22

System verilog number displays

Answer 22

2’b11 // 2 bit number with value 11

4’b1010 // 4 bit number with value 1010

8’b00110101 // 8 bit number with value 00110101

Question 23

How can the readability of numbers be improved?

Answer 23

Question 24

The support for numbers in different bases?

Answer 24

Question 25

How to sign values?

Answer 25

Whether a values is signed of not can make a difference to some operations. Use of the signed keyword in a definition makes the variable signed.

Question 26

How change values from signed to unsigned and visa versa?

Answer 26

Arithmetic is automatically signed if all variables passed to the operator are signed. An unsigned value can be converted to signed and vice versa:

signed’(variable)

unsigned’(variable)

Question 27

Example of signed numbers in system verilog?

Answer 27

Question 28

What is an enumerated type?

Answer 28

An enumerated type (enum) allows the definition of a new variable data type composed by a set of named values.

Question 29

Syntax and examples of enum?

Answer 29

Question 30

What are structures?

Answer 30

A structure type (struct) allows the creation of a compound variable i.e. a single variable that contains sub-variables.

Question 31

How are structures implemented?

Answer 31

Question 32

How are packages used in system verilog?

Answer 32

SystemVerilog uses packages to share definitions of new data types between modules. For this, the definitions are stored in a separate file, which is imported to each module that needs the created definitions.

Question 33

The differences between a System Verilog package and an imported package?

Answer 33

Question 34

How are tasks used in System Verilog?

Answer 34

SystemVerilog allows the use of Tasks to execute common processes. Tasks are useful to split large processes into smaller ones making the code clear, and easy to read and scale.

Question 35

Task syntax in system verilog?

Answer 35

Question 36

The function of the assign statement?

Answer 36

The use of an assign statement indicates the creation of combinatorial logic. Creates the logic for one wire or a bus of wires.

Question 37

Assign syntax?

Answer 37

Question 38

Key information regarding the assign command?

Answer 38

Any change on the right-hand side of “=“ will result in an update to the left-hand side. Each individual assignment will run all the time, executed concurrently and synthesised as separate logic circuits.

Question 39

What are bitwise logic operators?

Answer 39

Logic operators perform bitwise logic functions on individual bits. The logic operators can be used with a pair of wires or busses (vectors).

Question 40

Bitwise operators when vectors are of different length?

Answer 40

If the case of inputs vectors with the same length, each bit in the first vector is operated on by the bit in the same position from the second vector. If the vectors are not the same length, the shorter vector is padded with leading zeros.

Question 41

System Verilog bitwise operators?

Answer 41

Question 42

example bitwise logic

logic [3:0] a = 4’b0101;

logic [3:0] b = 4’b0000;

assign b = a > 1;

assign b = a >> 2;

assign b = a ^ a;

assign b = ~a;

Answer 42

logic [3:0] a = 4’b0101;

logic [3:0] b = 4’b0000;

assign b = a > 1; // right shift 1 bit, then b = 0010;

assign b = a >> 2; // right shift 2 bits, then b = 0001;

assign b = a ^ a; // a xor a, then b = 0000;

assign b = ~a; // not a, then b = 1010;

Question 43

Boolean logic in system verilog?

Answer 43

A Boolean logic operator is one that returns a value of TRUE (1) or FALSE (0) based on a logic operation of the input operations. These operations are used in decision statements.

Question 44

System Verilog boolean operators?

Answer 44

Question 45

Boolean operator examples:

!X

X&&Y

X||Y

Answer 45

!X // True if all values in X are 0, False otherwise

X&&Y // True if the bitwise AND of X and Y is all ones, False otherwise

X||Y // True if the bitwise OR of X and Y is all ones, False otherwise

Question 46

arithmetic operators system Verilog?

Answer 46

Question 47

relational operators?

Answer 47

A relational operator is one that returns a value of TRUE (1) or FALSE (0) based on a comparison of two inputs.

Question 48

The relational operators in system Verilog?

Answer 48

Question 49

What are conditional operators?

Answer 49

SystemVerilog has a conditional operator, ? : , also known as the ternary operator, that can be used to provide a more intuitive approach to modelling logic statements.

Question 50

The syntax for conditional operators?

Answer 50

Question 51

assign A = (B == 1) ? C : D;

assign F = (sel == 0) ? A : B;

Answer 51

// sets A to C if B is 1, D otherwise

// sets F to A if sel is 0, B otherwise

Question 52

Syntax for a multiplexer in System verilog?

Answer 52

Question 53

What is used in complex decision making?

Answer 53

When complex decision making is needed, different operators can be combined together with the conditional operator.

Question 54

Example of combining operators?

Answer 54

assign A = ((B == 1) && !(C > 4)) ? D : E;

assign F = (!C && (!A || B)) ? 1’b1 : 1’b0;