3 The Module data types and operators Flashcards
System Verilog Module?
A SystemVerilog design describes the hardware module of a system. This design, which will carry out some function, will eventually be synthesised into hardware.
The main component of a SystemVerilog design is the module which includes the interface to the system and description of the behaviour.
Module diagram with inputs and outputs?
System verilog internal module structure?
Example of a logic gate AND with 2 input bits.
SystemVerilog supports four basic values that a signal can take on:
SystemVerilog supports four basic values that a signal can take on: 0, 1, X and Z. The data types in SystemVerilog store these values.
Net Data types?
Net data types model the interconnection between components and can take values 0, 1, X and Z. The most common net data type is the wire.
Variable data types?
SystemVerilog contains many types that model storage which are called variable data types. These data types hold the value assigned to them until their next assignment.
The most important variable data type?
The most important variable data type is logic, which is 4-valued and allows to represent values 0, 1, X, Z, and is useful to create warnings in simulations if a value is not set.
What are busses?
- It is often necessary to handle multi-bit values (busses).
- SystemVerilog allows to create busses or vectors, which are one-dimensional array of elements.
- Net data types and variable data types can be used to create busses.
Syntax required to create busses or vectors?
wire [7:0] Sum;
// 8-bit vector called ‘Sum’ of type wire. MSB
// has the index 7 and LSB has the index 0.
logic [15:0] Q;
// 16-bit vector called ‘Q’ of type logic.
logic [11:0] address;
// This defines a 12-bit vector called ‘address’
// of type logic.
How can individual bits within the vector be addressed?
Individual bits within the vector can be addressed using their index.
address[0]; // This is the least significant bit of the vector ‘address’
address[11]; // This is the most significant bit of the vector ‘address’
address[6]; // This the 7th bit of the vector ‘address’
How can groups of bits be addressed?
Using an index range
address[3:0]; // This is the lower 4 bits of the vector ‘address’
address[11:8]; // This is the upper 4 bits of the vector ‘address’
What are arrays?
SystemVerilog also allows to create multidimensional arrays of elements, which can be seen as a “vector of vectors”. Vectors within the array all have the same dimensions.
Syntax required for array configuration?
Logic [7:0] Mem [0:9];
// Defines an array of 10 vectors of type logic,
// where each vector is composed of 8 bits
Integer A [0:99];
// Defines an array of 100 integers
Mem Map?
logic [7:0] Mem [0:9];
Numbers in SystemVerilog use the following syntax:
<size_in_bits>'<base></base>
<value></value></size_in_bits>
System verilog number displays
2’b11 // 2 bit number with value 11
4’b1010 // 4 bit number with value 1010
8’b00110101 // 8 bit number with value 00110101
How can the readability of numbers be improved?
The support for numbers in different bases?
How to sign values?
Whether a values is signed of not can make a difference to some operations. Use of the signed keyword in a definition makes the variable signed.
How change values from signed to unsigned and visa versa?
Arithmetic is automatically signed if all variables passed to the operator are signed. An unsigned value can be converted to signed and vice versa:
signed’(variable)
unsigned’(variable)
Example of signed numbers in system verilog?
What is an enumerated type?
An enumerated type (enum) allows the definition of a new variable data type composed by a set of named values.
Syntax and examples of enum?
What are structures?
A structure type (struct) allows the creation of a compound variable i.e. a single variable that contains sub-variables.
How are structures implemented?
How are packages used in system verilog?
SystemVerilog uses packages to share definitions of new data types between modules. For this, the definitions are stored in a separate file, which is imported to each module that needs the created definitions.
The differences between a System Verilog package and an imported package?
How are tasks used in System Verilog?
SystemVerilog allows the use of Tasks to execute common processes. Tasks are useful to split large processes into smaller ones making the code clear, and easy to read and scale.
Task syntax in system verilog?
The function of the assign statement?
The use of an assign statement indicates the creation of combinatorial logic. Creates the logic for one wire or a bus of wires.
Assign syntax?
Key information regarding the assign command?
Any change on the right-hand side of “=“ will result in an update to the left-hand side. Each individual assignment will run all the time, executed concurrently and synthesised as separate logic circuits.
What are bitwise logic operators?
Logic operators perform bitwise logic functions on individual bits. The logic operators can be used with a pair of wires or busses (vectors).
Bitwise operators when vectors are of different length?
If the case of inputs vectors with the same length, each bit in the first vector is operated on by the bit in the same position from the second vector. If the vectors are not the same length, the shorter vector is padded with leading zeros.
System Verilog bitwise operators?
example bitwise logic
logic [3:0] a = 4’b0101;
logic [3:0] b = 4’b0000;
assign b = a > 1;
assign b = a >> 2;
assign b = a ^ a;
assign b = ~a;
logic [3:0] a = 4’b0101;
logic [3:0] b = 4’b0000;
assign b = a > 1; // right shift 1 bit, then b = 0010;
assign b = a >> 2; // right shift 2 bits, then b = 0001;
assign b = a ^ a; // a xor a, then b = 0000;
assign b = ~a; // not a, then b = 1010;
Boolean logic in system verilog?
A Boolean logic operator is one that returns a value of TRUE (1) or FALSE (0) based on a logic operation of the input operations. These operations are used in decision statements.
System Verilog boolean operators?
Boolean operator examples:
!X
X&&Y
X||Y
!X // True if all values in X are 0, False otherwise
X&&Y // True if the bitwise AND of X and Y is all ones, False otherwise
X||Y // True if the bitwise OR of X and Y is all ones, False otherwise
arithmetic operators system Verilog?
relational operators?
A relational operator is one that returns a value of TRUE (1) or FALSE (0) based on a comparison of two inputs.
The relational operators in system Verilog?
What are conditional operators?
SystemVerilog has a conditional operator, ? : , also known as the ternary operator, that can be used to provide a more intuitive approach to modelling logic statements.
The syntax for conditional operators?
assign A = (B == 1) ? C : D;
assign F = (sel == 0) ? A : B;
// sets A to C if B is 1, D otherwise
// sets F to A if sel is 0, B otherwise
Syntax for a multiplexer in System verilog?
What is used in complex decision making?
When complex decision making is needed, different operators can be combined together with the conditional operator.
Example of combining operators?
assign A = ((B == 1) && !(C > 4)) ? D : E;
assign F = (!C && (!A || B)) ? 1’b1 : 1’b0;
