4 Behavioural descriptions and combinational logic

Question 1

What is Behavioural description?

Answer 1

Behavioural description: circuit design method that specifies the behaviour of the circuit rather than the architecture of the circuit.

Question 2

What is a structural description?

Answer 2

Structural description: explicit definition of how a circuit is constructed using multiple instantiation of modules.

Question 3

Example of structural description for multiplexer?

Answer 3

Question 4

Example of behavioral description? MUX?

Answer 4

Question 5

System verilog blocks to deal with behavioral descriptions?

Answer 5

SystemVerilog has three specialised blocks for Verilog descriptions: always_comb, always_latch and always_ff

Question 6

always_comb?

Answer 6

The always_comb statement can be used to split combinatorial logic into a flow of sequential instructions.

The sequence of commands to be executed is written between a begin and end statements.

Question 7

Example of use of always_comb blocks?

Answer 7

Question 8

Use of always_comb in System Verilog with graphing?

Answer 8

Question 9

For loops in system verilog?

Answer 9

• A for loop provides the ability to create a loop that can automatically update an internal variable.
• The loop will execute as long as a Boolean condition associated with a loop variable is TRUE.
• The starting value of the loop variable is provided using an initial assignment

Question 10

Uses of For loops?

Answer 10

• A for loop inside an always block allows easy duplication.
• A begin-end pair are used to create the looped set of statements
• An integer is declared as a loop variable.

Question 11

Loop syntax?

Answer 11

Question 12

Counter using a loop?

Answer 12

Question 13

The need for if-else?

Answer 13

An if-else conditional statement provides a way to make conditional signal assignments based on Boolean conditions.

Question 14

The use of an if statement?

Answer 14

The if portion of statement is followed by a Boolean condition that if evaluated TRUE will cause the signal assignment listed after it to be performed. If the Boolean condition is evaluated FALSE, the statements listed after the else portion are executed.

Question 15

multiple statements used with if?

Answer 15

If multiple statements are to be executed, then the statement uses begin-end keywords.

The if statement is similar to the ? : conditional operator

Question 16

Example if-else statement

Answer 16

Question 17

Example elseif structure?

Answer 17

Question 18

The case statement?

Answer 18

• A case statement is another technique for modelling based on Boolean conditions. This method is similar to the switch-case statement in programming languages such as C.
• Only one case executes depending on which value matches the condition.
• The case statement can be based on multiple input signal names by concatenating the signals within the parenthesis.
• The keyword default can be used to provide the desired signal assignment for any input codes not explicitly listed

Question 19

Case statement with one input signal

Answer 19

Question 20

Case statement with multiple input signals

Answer 20

Question 21

System Verilog casez statement?

Answer 21

• SystemVerilog provides the casez statement to handle Z values as don’t cares in the input conditions.
• The symbol ? can be used instead of Z.
• It is important to include the default value to prevent latches being synthesised.

Question 22

Example of casez coding?

Answer 22

Question 23

What are parameters in System Verilog?

Answer 23

Parameters can be used to scale a design

• The list #(parameter name=value …) is added into the module definition before the ports.
• The named parameters are used in for-loops etc. to scale the design.
• The default parameter value can be over-ridden in the instantiation.

Question 24

Example of delay parameters?

Answer 24

Question 25

Use of parameters to develop generic descriptions that are scalable and reusable.

Answer 25