21 Interfaces(NOT ASSESSED) Flashcards
Why interface?
It is easy to end up with systems in which many signals are passed between two blocks. SystemVerilog provides an Interface construct, which offers a new paradigm for modelling large and complex design. The interface construct allows signals to be collected together even though they are moving in different directions
How are modules grouped together?
Instantion, long-winded process?
Instantiation problems?
- Ports name, types and mode are defined in multiple modules.
- Tedious and redundant process.
- There is a risk of mismatch declarations in different modules.
- Even a small change in the design specification can require modifications in multiple modules.
- Not problems approach for reusability in other projects.
What does an interface allow you to do?
- An interface allows the encapsulation of signals into a block, which is known as encapsulation of communication
- The grouped signals can be represented as a single port
- All related signals are grouped together to form an interface
- They improve the maintainability and readability of designs, and reduce the amount of code require to model a design.
- They can contain parameters, variables, constants and assignments
- The interface allows reusability in other projects
A module may have more than one interface
Syntax for interface declaration:
Master and Slaves?
The interface sBus?
How are the ports defined on bus?
Overall bus script?
Overall interface design?
It is possible to define the modport in the definition of the module.
master module
It is possible to define the modport in the definition of the module. The master module will use the port configuration from masterPorts defined by modport in the interface. This configuration is accessed with “.” followed by the modport configuration.