T1 - Architecture of the CPU/ Performance

Question 1

CPU

Answer 1

• The CPU processes instructions

Question 2

Stored program concept

Answer 2

• In 1943-44, von Neumann had the idea of storing the program
  instructions/data in memory

Question 3

Von Neumann architecture

Answer 3

• Program instructions and data are both stored in the same memory

Question 4

Control unit

Answer 4

• coordinates activities in CPU
  -sends signals to control how data moves around
  Receives signals from the system clock
  Directs timing + controls other parts of the CPU

Question 5

Arithmetic logic unit

Answer 5

• actual arithmetic operations are done
  Carries out logical operations: AND, OR and NOT

Question 6

Registers -

Answer 6

very fast memory location in the CPU

Question 7

Cache

Answer 7

• it is slower to access than registers but faster than RAM

Question 8

Types of Registers: Program Counter (PC)

Answer 8

• holds the address of the next instruction to be executed

Question 9

Types of Registers: Memory Address Register (MAR) -

Answer 9

holds the memory address of the current instruction, so that these can be fetched from memory

Question 10

Types of Registers: Memory Data Register (MDR)

Answer 10

holds the actual instruction, and data that has been fetched from memory

Question 11

Types of Registers: Accumulator

Answer 11

• holds the result of an instruction before it is transferred to memory
  -result if alu

Question 12

FDE cycle

Answer 12

FETCH – fetches the next instruction + data involved to main memory
DECODE – decodes the instruction
EXECUTE – the instruction is executed

Question 13

PC : role

Answer 13

holds the address of the next instruction to be executed
incremented (increased by 1) as soon as that instruction has been fetched = moves onto next instruction.

Question 14

ACC : role

Answer 14

where arithmetic/ logic results are temporarily stored

Question 15

MAR during FETCH stage:

Answer 15

address of the next instruction is copied from PC to MAR.

Question 16

MDR during FETCH stage

Answer 16

instruction at that address is fetched from memory + copied to MDR

Question 17

Then the Control Unit during FETCH stage

Answer 17

decodes the instruction and decides if data needs to be fetched

Question 18

Factors affecting CPU performance:
Clock speed

Answer 18

• Cycles per second measured in hertz

Question 19

Processor cores -

Answer 19

The number of duplicate processing units (cores) placed in one CPU

Question 20

Cache

Answer 20

Memory on the CPU that is faster than RAM but slower than registers

Question 21

Factors affecting CPU performance:

Answer 21

cache
processor cores
clock speed

Question 22

clock speed role

Answer 22

Everything in a computer happens on the pulse of the internal clock
The faster the clock speed, the faster the instructions are processed

Question 23

Processor speed: Hz, KHz, MHz, GHz

Answer 23

One cycle per second = 1 hertz (Hz) = 1 instruction carried out each second
1 kilohertz (kHz) = 1000 cycles per second
1 Megahertz (MHz) = 1,000,000 cycles per second
1 Gigahertz (GHz) = 1,000,000,000 cycles per second

Question 24

Multi- core processors:
A dual-core processor

Answer 24

• can perform two instructions at the same time
• allows twice as many instructions to be executed,
• each core is theoretically able to process a different instruction at the same time with their own FDE cycles

Question 25

Cache Memory: role

Answer 25

a small amount of very fast, expensive memory in the CPU
It can be accessed faster than regular main memory (RAM)
Quickens fetch stage

Question 26

Level 1 cache -

Answer 26

extremely fast but small (between 2-256KB),
located on the CPU. Each core will have its own level 1 cache

Question 27

Level 2 cache -

Answer 27

usually also given to each core.
Is fast, but a little slower than level 1 cache.
The typical size is 256KB-8MB

Question 28

Level 3 cache -

Answer 28

slowest type of cache, but still faster than RAM.
It is usually located on the CPU
Stores 4MB-50MB.

Question 29

is cache shared

Answer 29

The cache is shared between all the cores on the processor

Question 30

Embedded Computers:

Answer 30

a single microprocessor:
that includes RAM, ROM and a CPU
frequently used to control a device using simple inputs