131 Week 5 - Memory

Question 1

Volatile memory

Answer 1

Memory that loses its contents when it loses power

Question 2

Non-volatile memory

Answer 2

Memory that keeps its contents when it loses power

Question 3

Dynamic memory

Answer 3

A type of volatile memory used for main memory
It is slower but cheaper than static memory.

Question 4

Static memory

Answer 4

A type of volatile memory used for registers and cache
It is fast but more expensive than dynamic memory.

Question 5

How is main (dynamic) memory organised?

Answer 5

Lots of locations which each store 1 unit of information/data.
Each location has an address it can be identified by.
Addresses are usually linear addresses - 0,1…n

Question 6

Address decoding

Answer 6

Memory is usually split up into chips.
An address decoder maps from a linear address to a specific chip and address within the chip.

Question 7

How can multi-byte words be organised?

Answer 7

Big endian or little endian

Question 8

Big endian

Answer 8

The byte with the lowest address stores the most significant byte.

Question 9

Little endian

Answer 9

The byte with the lowest address stores the least significant byte.

Question 10

Combinatorial logic

Answer 10

Its outputs are purely a function of its inputs

Question 11

Sequential logic

Answer 11

Its outputs are a function of its inputs and of its current outputs

Question 12

S-R flip flop

Answer 12

A sequential logic circuit that can store a the state of a bit.
Has 1 output: Q
Has 2 inputs:
Set (S) - if set is high, Q will be stored as high.
Reset (R) - if reset is high, Q will be reset and store low.
When S or R returns to low after the high pulse, Q will stay where it is.
Cannot have S and R high at the same time.

Question 13

Limitations of S-R flip flop

Answer 13

Needs distinct Set and Reset inputs where ideally there is 1 input that sets the state.
Cannot specify if we want input data to be stored or not when ideally there is a “latch” that states if the input should be stored or not.

Question 14

Clocked D-type flip flop

Answer 14

Variation on clocked d-type flip-flop.
Has 1 output: Q
Has 2 inputs:
Data: the input to be stored.
Latch: if the data should be stored or not.

Question 15

Limitations of clocked D-type flip-flop

Answer 15

Cannot control when the data leaves the circuit - ideally want an output enable (OE) signal on the end of the circuit.

Question 16

Master-slave flip-flop

Answer 16

Variant on the clocked D-type flip flop.
Has an output enable signal which controls when data leaves the circuit.
Has 2 sides - the master and slave
When master latch is high, data input is stored in the master side.
When master latch returns to low, it allows the slave side to store the input from the master side.

Question 17

Reasons for a master slave flip flop

Answer 17

Allows data to leave the circuit before new data is let in meaning there is no chance of data being overwritten before it can be used.

Question 18

Master-slave flip-flops to create registers

Answer 18

Registers can be created from master-slave flip-flops by connecting latch and output enable inputs of flip flops so they can be used together.

Question 19

Busses

Answer 19

Connects components within the CPU and allows information to be transferred between them.
Bus wires are shared so only there can only be 1 active output at a time - the reason we need output enable.

Question 20

Address bus

Answer 20

Runs between the control unit and main memory and is used to tell main memory to access a specific address to be read from or written to.
It’s width corresponds to how many addresses it can access.

Question 21

Data bus

Answer 21

Carries data around the computer.
An n-bit processor will have a data bus of n bits wide.
Some processors have external and internal address busses with external busses being less wide to reduce costs.