131 Week 17 - Exceptions Flashcards
Exception
An unscheduled function call that branches to a new address. It allows a CPU to notify your program to implement code that manages external events.
They can be caused by software or hardware. E.g., user presses a key on keyboard (hardware exception) or encountering undefined instruction.
Exception types
Synchronous exceptions - caused by an instruction in the running program. E.g., Arithmetic exceptions, invalid memory addresses in load/store, trap instructions.
Asynchronous exceptions - caused by an I/O device requesting the processor. Known as a hardware interrupt. E.g., pressing a micro:bit button causes the OS to interrupt the running code to service the interrupt.
CPU privilege levels
Computers do not allow access to full resources to any code as buggy code could corrupt systems.
The CPU limits resource access to different processes depending on its privilege level.
System calls
A type of software exception that invokes a service OS, running at a higher privilege level.
Allows user code to request system resources as they are handled by the OS which is seen as a trusted provider.
Transitioning between privilege levels
- SVC instruction is called using the relevant supervisor instruction (SVC in ARM). Execution is paused.
- The system call is identified and the kernel function based on the system call is executed.
- System call returns values.
- Execution resumes.
Managing exceptions
An exception will create an execution interrupt for the CPU. The process looks like a special function but the function is called by the CPU rather than your program.
- Before starting a new FDE cycle, check if there is a pending interrupt.
- If there is an interrupt, stop normal cycle (fetch-decode-execute).
- Save current CPU state, i.e. registers.
- Run user code to manage interrupt.
- Change code execution to interrupt handling code.
Vector table
A table used to find the appropriate exception handler for an exception.
It maps exception types to their corresponding handler routines.
Contains a branch instruction to an exception handler then returns to user code.
Instructions to handle exceptions are stored low in memory at 0x00000018
Current Program Status Register (CPSR)
An ARM register that records the state of the program. Any arithmetic instructions will update its value.
Made up of:
I bit – “IRQ flag”: disable IRQ interrupts.
F bit – “FIQ flag”: disable FIQ (Fast IRQ) interrupts.
T bit – “Thumb flag”: Disable thumb mode.
Mode: Current execution mode.
Exception Handling
- Store the CPSR (current program status register) to SPSR (saved program status register).
- Set execution mode and privilege level based on exception type.
- Disable interrupts using the interrupt mask bits in CPSR to stop new exceptions to be handled before the current exception has been handled.
- Store return address into banked lr (link register).
- Push other registers to the stack to preserve them.
- Branch to the exception function based on the address from the vector table.
- Execute the exception handler.
- Copy lr to pc and banked spsr to cpsr to return the program to its state before handling the exception.
- Pop the registers back of the stack to return the registers to their states before handling the exception.
ARM execution modes
ARM processors can operate on one of several different execution modes. Each mode has different privilege levels.
User mode operates at PL0 (user) and is the lowest privilege level.
Others modes operate at PL1 (kernel) which can access all system resources.
There are many different kernel modes each with different privileges and uses.
System Control Unit (SCU)
Handles various system-level operations, like power management and reset control.
System control register (SCR): Controls sleep modes (sleep, deep sleep).
Configuration and Control Register (CCR): controls stack alignment and unaligned memory access behaviour.
Configurable Fault Status Register (CFSR): provides details of the current hard fault.
BusFault Address Register (BFAR): stores bus address that caused the error.
BusFault Status Register (BFSR)
BFSR is a part of the CFSR and contains the register that explains the nature of the error.
STKERR/UNSTKERR: Error with the stack.
PRECISERR: Error Mem address is in BFAR.
IBUSERR: Error reading instruction.
BFARVALID: Records if this is a BusFault
Fast Interrupt Execution Mode (FIQ)
A fast, low-latency interrupt handling mechanism in high-end ARM. It uses banked registers to copy values
from actual registers on an interrupt resulting in faster interrupt handling.
