131 Week 4 - Instruction Set Architecture

Question 1

Instruction set architecture

Answer 1

A set of commands that a processor can understand and execute - the interface between the hardware and software.

Question 2

Reduced instruction set architecture (RISC)

Answer 2

Small number of instructions with a common operand format.
Most instructions operate on registers
Typically take 1 clock cycle to execute.

Question 3

Fetch decode execute cycle

Answer 3

A constantly repeating cycle within the CPU of fetching, decoding them executing instructions.

Question 4

Registers

Answer 4

Very fast bits of memory within the CPU that are used as holding areas for data being worked on inside the CPU.
Arithmetic and logic instructions are often designed to only work on registers.

Question 5

General purpose register

Answer 5

Registers used by the arithmetic and logic instructions which do not have a fixed purpose

Question 6

Specific purpose register

Answer 6

Registers which have a single fixed purpose e.g., program counter

Question 7

Program counter (PC)

Answer 7

Special purpose register that acts as a pointer to the next instruction to be executed.

Question 8

How is PC changed

Answer 8

Either incremented by default during FDE cycle or can be explicitly changed using control transfer instructions to point it to a specific address.

Question 9

Handling subroutines

Answer 9

Before executing the subroutine, processor notes the value of PC - the return address.
Processor jumps to the start of the subroutine and runs it
At the end of the subroutine processor retrieves return address and continues execution from there.

Question 10

Call stack

Answer 10

The call stack allows execution of nested subroutines by pushing and popping return addresses of subroutines to the stack when they are called and when they have finished executing.