131 Week 5 - Control Unit Flashcards
What does the control unit (CU) do?
Controls and sequences the other architectural modules (mostly ALU and main memory) using their respective control lines.
It’s driven by a “clock” which gives regular electric pulses or “ticks” and endlessly executes the FDE cycle
How does the control unit control registers and the ALU?
Latch and output enable control lines for registers and function select, shift L/R and carry in for the ALU
Instruction register
A special register that holds the instruction that is currently being executed.
Memory address register (MAR)
A special purpose register that holds the memory address which the processor will write to/ read from depending on the instruction.
Memory data register (MDR)
A special purpose register that holds data going to/ coming from the memory address held in MAR.
Finite state machine
A way of implementing the FDE cycle.
It is a hard wired sequential logic circuit built in terms of NAND gates.
It is high performance but expensive and hard to evolve.
Microcode
A way of implementing the FDE cycle.
It is a sequence of micro-instructions in a micro-memory.
It is slightly lower performance but much more flexible as manufacturers can easily add new instructions.
Opcode
Specifies the operation to be performed on the data
Operand
The data to be acted on or the memory location of the data in a register.
Pipelining
A way to speed up the fetch decode execute cycle by overlapping instructions so that different instructions can use different parts of the CPU simultaneously.
Pipeline hazards
Situations that cause the pipeline to stall and slow down. The pipeline then needs to be flushed to be able to continue.
They can be categorised into control, data and structural hazards.
Control hazard
A control transfer instruction changes the flow of execution and therefore what instructions need to be executed next.
This means the semi-executed instructions in the pipeline are not needed yet and different instructions are now needed to be executed.
Data hazard
When an instruction depends on the outcome of the previous instruction or when 2 instructions on the pipeline needs to access the same data.
Structural hazards
When 2 parts of the pipeline need to access the same piece of hardware (e.g., ALU, address decoder)
