131 Week 13 - Assembly intro Flashcards

1
Q

Instruction set architecture (ISA)

A

The view of the processor that is seen by programs being executed.
It specifies the set of available instructions, registers, their formats, expected inputs etc.

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2
Q

Acorn RISC Machine (ARM)

A

An assembly language that uses VonNeuman architecture and RISC architecture.
VonNeuman: CPU architecture that stores instruction and data in the same memory.
RISC: Small, highly optimized instruction set which keeps pipeline simple but raises complexity in software. Power and heat efficiency

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3
Q

Aim of ARM

A

lower of the compiler to the hardware level
Do not raise hardware to the software level (as with CISC)

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4
Q

What bit architecture is ARM

A

32-bit architecture which defines the range of values in basic arithmetic (how big an integer is), number of addressable bytes (2^32 bytes) and the width of a standard register.

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5
Q

Label

A

A symbolic name assigned to a memory location or instruction, making it easier to reference and manage code.

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6
Q

Directive

A

Assembler directions or setting changes. They are not instructions and are not included in machine code.
Begins with with a “.”
Must exist on separate lines to other directives.
They can define symbols, Data & regions, control flows,
generate reports and define assembly parameters.

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7
Q

Comment

A

Comment a line using @

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8
Q

Instruction

A

The actual commands that the CPU executes.
They operate on registers, memory, and input/output devices.
Most basic unit of computer processing

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9
Q

Registers

A

Most fundamental storage area on the chip.
Can carry many data types, must be 32 bits long
Needed to process data in ARM as the ALU cannot access data straight from main memory.
ARM CPU has 16 registers.

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10
Q

ARM registers

A

Registers are represented with a 4-bit number
R0-R12: can be used to store data by the user
R0-R7: Low registers
R8-R12: High registers - specific instructions store data to them
automatically.
R13: Stack pointer
R14: Link register
R15: Current Program Status Register (CPSR) - CPU Status register on co-processor.

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11
Q

Instruction format

A

OPERATOR, DestinationRegister, SourceRegister, SourceRegister @Comments
E.g.,
ADDS r0, r1, r2 @r0 = r1 + r2
or
ADDS r0, r1 @r0 = r0 + r1

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12
Q

Assembler

A

Converts human readable assembly into binary.
Platform specific.
Assembler does not do any smart decision making – one-to-one match between instruction and 16-bit binary format.

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13
Q

Pseudo-instructions

A

Assembler instructions which do not have direct machine code equivalent but make programming easier. They are converted into multiple machine code statements by the assembler.

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