131 Week 17 - Memory Mapped IO Flashcards
Memory mapped IO
A mechanism for the CPU to interact with IO devices using memory addresses.
Hardware device registers (GPIO, UART) are mapped to specific memory addresses which the CPU can then interact with hardware by reading/writing to these addresses.
IO bus
The bus used to interface the CPU and peripheral devices.
Devices attach to the IO bus using IO modules and interfaces.
IO modules
A hardware component that manages the transfer of data between the CPU and peripheral devices
IO interface
The intermediary logic that connects the CPU/system bus to an I/O module or peripheral. It provides a standardized way for devices to communicate with the processor by defining how different hardware components connect at the electrical/signal level.
It makes sure that the device is ready for the next batch of data and that the host is ready to receive the next batch of data from the peripheral device.
Protocol
The form and meaning of the signals exchanged between senders and receivers. Signals can either be command or data signals.
Handshake
A protocol exchange where the receiver sends a signal to either acknowledge commands/data that was sent or to say it is ready to receive data.
IO register
An IO register is the memory address associated with the IO device.
How does MMIO work
IO devices and memory share the same address space. Each IO device has its own reserved block of memory.
Data transfers to/from the IO device is done by moving bytes to/from the memory address mapped to the device.
From the programmers perspective, MMIO is like using regular load/store instructions making it simple and convenient for the programmer.
What memory addresses are used for MMIO operations
Typically 0x40000000-0x60000000 is used for MMIO operations.
Polled IO
The CPU monitors a control/status register associated with a port by repeatedly checking the status (polling) of a control bit . When a byte arrives in the port a bit in the control register is set.
If, when the CPU polls the control bit and it is set, the CPU will reset the control bit, receive the byte and processes it then resumes polling the register as before.
Interrupt driven IO
Instead of constantly polling a register, the CPU waits for an IO device to send an interrupt.
When an IO device sends an interrupt, it pause regular execution to handle the exception from the IO device, then returns to regular execution once the interrupt has been handled.
IO devices can be configured whether to interrupt for every word or for an entire batch of data - configurable granularity.
GPIOTE
An exception handler for Nordic Semiconductor’s nRF series microcontrollers. Can be used for interrupt driven IO on microbits.
