Verification Tools

Question 1

What are two names for the extracted files that LVS compares?

Answer 1

1. netlist (SPICE)

2. circuit file

Question 2

What does VLDB stand for?

Answer 2

Verification Logic Data Base, file format for netlists

Question 3

What are parametric checks?

Answer 3

Checks on device parameters: W L R C

Question 4

What are the four main types of LVS errors?

Answer 4

1. Nets
2. Devices
3. Pins
4. Parameters

Question 5

What does CDL stand for?

Answer 5

Circuit Description Language, standard language that net lists are written in.

Question 6

What are two other names for schematic entry?

Answer 6

Design entry, schematic capture

Question 7

What is the Cadence schematic entry tool called?

Answer 7

Virtuoso Schematic Composer

Question 8

What does PDV stand for?

Answer 8

Physical Design Verification tools

Question 9

List nine types of verification tools.

Answer 9

1. DRC
2. LVS
3. SCHECK
4. Antenna Rule Check
5. Electrical rule check (ERC)
6. Latch-up check (taps)
7. XOR - Layout vs. Layout (LVL), used after ECO
8. Layout Parasitic Extraction
9. Layout vs. Silicon (LVSi or SiVL)

Question 10

What does ERC stand for, and how does it work?

Answer 10

Electrical Rule Check. Very basic, no schematic (netlist) needed, 2 pins on same wire, internal net must have path to power and ground.

Question 11

Name some stand-alone verification tools and the companies that make them.

Answer 11

Calibre (Mentor)
Hercules (Synopsis)
Dracula (Cadence)

Question 12

What are the basic procedures to run Dracula LVS?

Answer 12

LOGLVS
cir transceiver.netlist_01
con bias
x
(generates LVSLOGIC.DAT. Error file: PRINT.OUT)
PDRACULA
/g draculaLVS.rul
/f
(generates jxrun.com)
jxrun.com