Chip-level Flashcards
What are the basic stats of our final project?
Die area: 48.1 mil^2 Die size: x = 169.28um = 6.67mils y = 183.18um = 7.2mils # of devices: 10k # of gate counts (logics): 2.5k Drawn layers: 16 Generated layers: 5
What are nine general guidelines required in performing chip-level floor-planning.
- Understand top-level schematic.
- Bonding pad assignment (pad ring) information. Comes from packaging and marketing groups.
- Chip aspect ratio and area.
- Block placement constraints. Blocks heavily interfacing with each other near each other. Near appropriate bond pads. Keep in mind speed and IR drop, etc.
- Required P&G widths.
- Clock, high-speed, critical nets. Shorter and / or wider metal traces.
- Placements of process and product related structures.
- Placements of extra (dummy) devices, engineering test circuits and / or PCM.
- OPC
What does OPC stand for?
Optical Proximity Correction
What are hammerhead, serif, and assists/bias?
Used in OPC. Hammerhead to compensate for line-end shortening. Serifs are additions or removals to corners to compensate for corner rounding. “Assists” or “bias” used to address line width narrowing issue.
What is “engineering tape-out” or “engineering run”.
One early tape-out allowed by FAB.
What does PCM stand for?
Process Control Monitor. Structures for testing via reliability (“via chain”), logic speed (ring oscillator), Van der Pauw method of determining sheet rho.
List 9 process and product related structures.
- Copyright and Maskright symbols.
- Chip ID (or product name)
- Company Logo
- Initials of designer.
- Mask Revision ID’s (or layer ids)
- Critical Dimension (CD) bars (common shape is tuning fork)
- Alignment targets.
- Scribe line.
- Seal ring.
What’s another possible usage of the term “seal ring”?
Special guard rings biased at a special voltage other than power or ground.
What layers typically make up the scribe line?
nwell, ndiff (or pdiff), contact, all vias, vapox
Name three problems that OPC attempts to solve.
- Corner-rounding effect
- Line width narrowing issue
- Line-end shortening effect
Name three possible solutions to SiVL problems.
- OPC
- Double patterning
- Wave shifting.
What is an “abstract view”?
Placeholder cell with estimated size and pins. For the router.
Name three Cadence P&R tools.
- Encounter
- CCAR
- Cell Ensemble (good for standard cells)
What does CCAR stand for?
Cadence Chip Assembly Router
What company originally created Dracula?
ECAD
