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Analog Flashcards

1
Q
  1. What’s another name for “digital”?

2. What are two other names for “analog”?

A
  1. Binary

2. Linear, “small signal circuit”

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2
Q

What types of waves do digital and analog use?

A

Digital: square
Analog: sinusoidal, triangular, saw-tooth

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3
Q

Name five differences between digital and analog.

A
  1. Digital layouts are large, analog are small
  2. Digital requires more wires, metal layers
  3. Digital requires few passive devices
  4. Digital: small feature sizes and tight design rules to minimize chip size. Analog: for precision reasons, larger feature sizes and looser design rules.
  5. Digital: matching occasionally. Analog: matching very common and critical.
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4
Q

What does DAC and ADC stand for?

A

Digital to Analog Converter, Analog to Digital Converter

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5
Q

Why are analog circuits vulnerable to interference and process variations?

A

Much lower voltage or current levels. Matching often required, for instance differential pairs.

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6
Q

What three things must a matching circuit tolerate?

A
  1. Variations in process parameters.
  2. Variations in operating temperature.
  3. Variations in operating conditions such as supply voltage difference and voltage and current drifts due to interference.
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7
Q

What are 7 common layout techniques to allow an analog circuit to tolerate variations?

A
  1. Layout matching devices in the same orientation and close to each other.
  2. Layout matching devices in the same style (number of contacts, size of diffusions, etc.
  3. May require exact same input order as schematic even in “AND” configurations.
  4. Add dummies to eliminate the “edge effect” or “proximity effect”.
  5. Keep matching devices away from nwell edge to reduce Well Proximity Effect (WPE).
  6. Keep matching devices away from Trench Isolation Edges.
  7. Use inter-digitating technique.
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8
Q

Why layout matching devices in the same orientation and close to each other?

A

Minimizes deviations both in the distribution of dopants and the etching of materials among matching devices.

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9
Q

Why layout matching devices in the same style?

A

Minimizes parasitic R and C among matching devices.

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10
Q

Why should the input order match the schematic in many analog circuits?

A

Failing to do so will make the circuit performance less predictable because of variations in series resistance due to transistor’s body effect.

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11
Q

What is another name for the “edge effect”?

A

“Proximity effect”.

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12
Q

What is the edge effect and its solution?

A

Result of differing dopant concentrations and etching consistence on the devices along the perimeter of a large group of similar devices. Will result in a mismatch between inner and outer devices. Solution: dummies

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13
Q

What does WPE stand for?

A

Well Proximity Effect

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14
Q

What is the well proximity effect?

A

Dopant concentration is higher along the nwell edge because at the time of bombardment the photoresist along the edges of a well deflects some dopant ions.

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15
Q

What differences does the well proximity effect cause?

A

Threshold (Vt) and Ids, every kind of MOS.

Also carrier mobility, transistor gain, Leff and R.

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16
Q

What does STI stand for?

A

Shallow Trench Isolation

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17
Q

What is STI?

A

Trenches of SiO2 or Si3N4 surrounding devices.

18
Q

What problems does STI cause?

A

Proximity and Compressive Stress issues. Because of difference in lattice spacing between silicon regions (nwell or psub), STI induces stress. First order effect is to alter band structure, which changes effective mass of mobile electrons or holes, altering mobility. Also effects saturation velocity. Affects spacing of atoms in lattice, causes changes in final doping profiles in the body after annealing. Threshold voltage and body effect coefficient can therefore be indirectly altered.

19
Q

What does interdigitating do?

A

Offsets both dopant concentration variation and temperature gradient across the die surface by exposing both devices in an identical manner.

20
Q

When do you need to do wire matching? How do you do it?

A

When two or more interconnects require their parasitics to be matched. Use similar layers with similar lengths to form matching connections.

21
Q

Describe 4 different P&G mixed signal routing plans, from worst to best.

A
  1. Shared VDD and VSS bond pad, single tributary (rail) feeding all circuits.
  2. Shared VDD and VSS bond pad, separate rails for analog and digital
  3. Separate bond pads for avdd and avss.
  4. Separate avdd and avss bond pads, and separate rails for nwell and psub vs. transistors and devices.
22
Q

What is “crosstalk”?

A

Any unwanted interference from one conductor (or layer) to another. Between two conductors there exists mutual capacitance (Cm) and Inductance (Lm) which give rise to feedthrough (or coupling).

23
Q

What is the equation describing how propagating voltage couples (induces) current on a neighboring conductor?

A

Delta i = Cm * dv / dt, where delta i == coupled current, Cm is mutual capacitance between conductors, dv / dt == voltage change on source with respect to time.

24
Q

What is the equation describing how current induces voltage on a neighboring conductor?

A

Delta v = Lm * di / dt, where delta v = induced voltage, Lm is mutual inductance between conductors, di / dt == current change on source with respect to time.

25
Q

What layout and circuit techniques are used to reduce severity of crosstalk?

A
  1. Place concerned objects (layers or group of circuits) farther away from each other.
  2. Reduce overlapping area between objects.
  3. Employ wire shielding techniques.
  4. Add “slew” to smooth out signal transitions (leading and trailing edges). A circuit design trick.
26
Q

What are three common methods of wire shielding?

A

Parallel, Tandem, and Coax

27
Q

What is parallel shielding?

A

Shield wire runs parallel to the shielded wire on same layer.

28
Q

What is tandem shielding?

A

Shield wires overlap on layers above and below. Overhang is required.

29
Q

What is coax shielding?

A

Combination of parallel and tandem.

30
Q

What are solutions to Ground Bounce?

A
  1. Increase capacitance and decrease inductance of P & G rails. Make them wider and run them close together.
  2. Decrease IR drop. Again make them wider.
  3. On-chip or off-chip decoupling capacitors between rails.
  4. Replacing high current drivers with slew-rate limited ones.
31
Q

What are three main routes that noise from one area of a circuit can affect another area?

A
  1. Through regular wiring, such as ground bounce, or signal line sharing. Current spike causes voltage fluctuation due to IR drop.
  2. Through gaps among layers, such as noise among metals and polys. Coupling effect.
  3. Through nwell and psubstrate. A combination of IR drop along these highly resistive materials as well as extra carriers (holes and electrons) getting injected when transistors are switching.
32
Q

What causes nwell and substrate noise, and what is the best solution?

A

Parasitic capacitance and inductance between polys/diffusions and nwell/psub. Also IR drop along nwell and psub. Best solution is guard rings, which absorb injected carriers.

33
Q

What does DNW stand for? What is an alternate name?

A

Deep Nwell. Burried Nwell

34
Q

What is the purpose of DNW?

A

Controls the substrate leakage of NMOS and provides better isolation. Suppress noise-coupling injected by switching logics in mixed-signal environment, which inject noise that propagates along shared substrate. An OpAmp might accidentally amplify this noise.

35
Q

What are the common applications of DNW?

A

Common in high-speed, RF and mixed signal circuits.

36
Q

What are two benefits of DNW?

A
  1. Better noise isolation
  2. Achieve a stand-alone negative bulk bias for certain NMOS so they can serve as negative voltage switch. Common operating requirement in programmable products such as FLASH memory design.
37
Q

What are two main issues in matching?

A

How to make both sides equal, how to shield

38
Q

What are three levels of matching?

A

basic / moderate / accurate

39
Q

What’s more sensitive to interference, inputs or outputs? Which creates more noise?

A

Inputs (high impedance) more sensitive, outputs create more noise

40
Q

When is a transistor in “linear mode”?

A

When it’s operating between 0V and the saturation point, which is dictated by the gate voltage.

41
Q

Why is vss so important?

A

Because it’s the reference voltage for analog circuits.

42
Q

List types of P&G rails, from quiet to noisy

A

avss_tap, avss, vss, iovss

Layout (24 decks)

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