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Test 1 Flashcards

1
Q

Who discovered electrons?

A

Lorentz

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2
Q

When were electrons discovered?

A

1895

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3
Q

Who invented vacuum tubes?

A

De Forest

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4
Q

When were vacuum tubes invented?

A

1906

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5
Q

Who invented the BJT?

A

Shockley, Bardeen, and Brattain (awarded Nobel Prize)

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6
Q

What does BJT stand for?

A

Solid-state discrete Bipolar Junction Transistor

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7
Q

When was the BJT invented?

A

1950

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8
Q

Who invented integrated circuits and the monolithic (or planar) process?

A

Robert Noyce and Jack Kilby

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9
Q

When were integrated circuits invented?

A

1958

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10
Q

Who invented the FET?

A

Bell Labs

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11
Q

When was the FET invented?

A

1960

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12
Q

What does FET stand for?

A

Field effect transistor

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13
Q

What kind of charge do neutrons carry?

A

None

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14
Q

What kind of charge do protons carry?

A

Positive

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15
Q

What kind of charge do electrons carry?

A

Negative

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16
Q

How much heavier than electrons are protons and neutrons?

A

1800 times

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17
Q

What are the three elements of a circuit?

A

A group of electrical components connected by elecrical wires powered by a power supply.

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18
Q

What are some typical electical components (devices)?

A

Transistors, resistors, capacitors, diodes, inductors

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19
Q

What are some typical materials for electrical wires in IC?

A

Copper, aluminum

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20
Q

What are some typical power supplies?

A

Battery, household power outlets

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21
Q

What is a conventional (discrete) circuit?

A

All electrical components and wires are manufactured seperately (individually). Components are connected with wires through soldering.

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22
Q

What are integrated circuits?

A

All electrical components and wires are built and manufactured over the surface of a tiny piece of silicon.

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23
Q

What is a schematic?

A

A circuit drawing which shows details of building a circuit

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24
Q

What are the details of a schematic?

A

Types and number of components to use, and how to connect (hookup) these components.

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25
Q

What is a logic symbol?

A

A symbolic shape used to represent a functional circuit.

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26
Q

What are the two main categories of electrical devices?

A

Active and passive

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27
Q

Name some active devices.

A

Transistors, diodes

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28
Q

Name some passive devices.

A

Resistors, capacitors, inductors

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29
Q

What characteristic distinguishes active devices from passive ones?

A

Active devices can amplify.

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30
Q

What are the two main types of transistors?

A

MOSFETs and BJTs

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31
Q

What does MOSFET stand for?

A

Metal oxide semiconductor field effect transistor

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32
Q

What are the two types of MOSFETs? Give four different names.

A

P-channel MOSFET, PMOS, P-gate, pfet / N-channel MOSFET, NMOS, N-gate, nfet

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33
Q

What are the two types of BJTs?

A

NPN and PNP

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34
Q

Describe the symbols for the passive devices

A

Resistor = sawtooth / capacitor = break in line with T and bow / inductor = round tooth

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35
Q

What does the symbol for a diode look like?

A

Triangle with a line across the point (like an inverter with a line instead of a bubble)

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36
Q

How are diodes related to transistors?

A

A diode is a partial transistor with the collector not used.

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37
Q

What are the four terminals of a MOSFET?

A

Source, drain (interchangeable), gate, bulk

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38
Q

What are the three terminals of a BJT?

A

Collector, emitter, base (none interchangeable)

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39
Q

What are the three main types of integrated circuits?

A

CMOS (only MOSFETS and passive devices), BJT (only BJT and passive devices), BiCMOS (BJT + CMOS + passive devices)

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40
Q

What are two other names for a transmission gate?

A

Transfer gate, CMOS switch

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41
Q

What is an AND group / configuration?

A

Two or more transistors of the same type connected in series

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42
Q

What is an OR group or configuration?

A

Two or more transistors of the same type connected in parallel.

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43
Q

What is an electrical conductor?

A

A medium through which an electrical current can flow.

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44
Q

What are electrical conductors made of in IC?

A

Metal or semiconductor

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45
Q

What semi-conducting materials are used in IC?

A

poly, diffusions, nwell, and p-substrate

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46
Q

What non-conducting materials are used in IC?

A

Silicon Dioxide and Silicon Nitride

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47
Q

What is the chemcial symbol for Silicon Dioxide?

A

SiO2

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48
Q

What is the chemical symbol for Silicon Nitride?

A

Si3N4

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49
Q

What are other names for an electrical wire?

A

Node, net, signal, bus, line

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50
Q

What are names for a label associated with a wire?

A

Node name, wire name, net name, signal name

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51
Q

What is an electrical short?

A

When two conductors having different node names are accidentally connected (shorted) together

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52
Q

Is short always bad?

A

No short might just refer to a correct connection

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53
Q

What is a floating net?

A

Wires that the designer forgot to join

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54
Q

When is a conductor open?

A

When there is a break in connection

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55
Q

Is open always bad?

A

No, it can just refer to correctly breaking a node

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56
Q

What is the process called to fabricate an IC?

A

Planar or monolithic

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57
Q

What is the very top layer of insulator called on an IC?

A

Passivation layer

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58
Q

What is another name for an insulating material?

A

Dielectric

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59
Q

What are other names of the oxide layers?

A

CVD oxide, gate oxide, field oxide

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60
Q

What are the two ways of connecting materials?

A

Touching (or merging) materials of the same layer, or allowing materials at two adjacent levels to meet (touch) through a hole in the insulator

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61
Q

What are global nets?

A

Nets that travel everywhere on the chip and are heavily loaded

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62
Q

When should an AND be interpreted as a primitive logic?

A

When its load is not an OR or a NOR

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63
Q

When should an OR be interpreted as a primitive logic?

A

When its load is neither an AND nor a NAND

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64
Q

What are the benefits of complex logics?

A

Reduction in transistor sizeMore compact and simpler layoutTime saving in doing layoutCircuit speed improvementReduction in circuit power consumption

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65
Q

Steps to convert complex logic?

A
  1. Is this a complex logic?2. Identify final output (NAND or NOR), and draw it as primitive3. Identify logic symbols driving that primitive4. Replace each NMOS in the primitive with the correct AND or OR group5. Replace each PMOS with the complementary AND or OR group6. Correctly connect polys7. Repeat steps for each logic symbol in #3
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66
Q

Define cell.

A

A piece of layout drawing

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67
Q

Define block

A

A larger cell

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68
Q

Define mega cell or macro cell

A

A relatively large piece of layout, usually made of several smaller cells or blocks

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69
Q

Define die

A

An entire layout project or an actual design (chip) in silicon form. One die contains one project on it

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70
Q

Define die size

A

The physical dimension of a die. Normally measured in mills or microns

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71
Q

Define SSI

A

Small scale integration - small chips

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72
Q

Give an example of a SSI

A

The power management chip on a cell phone

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73
Q

Define MSI

A

Medium Scale Integration

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74
Q

Define LSI

A

Large Scale Integration

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75
Q

Define VLSI

A

Very Large Scale Integration

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76
Q

Define ULSI

A

Ultra Large Scale Integration

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77
Q

Give an example of a ULSI

A

A pentium chip

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78
Q

Define SOC

A

System on a chip - mega chips

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79
Q

Define tape out

A

The time when a project is completed

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80
Q

Define cell-library

A

Layout database which contains a collection of cells, blocks, etc., with unique cell names bundled together under a project (library) name

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81
Q

What is one millimeter relative to a meter?

A

1/1000 of a meter 10-3

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82
Q

What is one micrometer relative to a meter?

A

1 / 1,000,000 of a meter 10-6

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83
Q

What is one nanometer relative to a meter?

A

1 / 1,000,000,000 of a meter M-9

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84
Q

What’s one angstrom?

A

1 / 10,000,000,000 of a meter 10-10

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85
Q

What’s one milli-inch?

A

1 / 1000 of an inch 10-3 inch

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86
Q

What the abreiviation for millimeter?

A

mm

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87
Q

What’s the abbreviation for micron?

A

um

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88
Q

What’s the abrieviation for nanometer?

A

nm

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89
Q

What’s the abbrieviation for angstrom?

A

A with a little circle over it

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90
Q

What’s the abbreviation for a milli-inch?

A

mil

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91
Q

How many microns in 1 mil?

A

25.4

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92
Q

How many feet in 1 meter?

A

3.2808…

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93
Q

What’s another name for micrometer?

A

micron

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94
Q

What’s another name for micron?

A

Micrometer

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95
Q

What’s a PN junction?

A

Formed when P- or P+ touches N- or N+

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96
Q

When is a PN junction forward-biased?

A

When the P-material sees a higher voltage (potential) than the N-material does.

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97
Q

When is a PN junction reverse-biased?

A

When the P-material sees a lower voltage than the n-material does

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98
Q

What are other names for reverse-biased?

A

Back biased, reverse connected

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99
Q

What is formed when a PN junction is reverse-biased?

A

A depletion layer, which blocks the flow of current

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100
Q

What is the nwell typically connected to?

A

VDD

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101
Q

What is the p-substrate typically connected to?

A

VSS

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102
Q

Why must the nwell and p-substrate be connected to VDD and VSS?

A

To electrically isolate the nwell and p-substrate, so that operations of the p-gates does not interfere with operation of the n-gates and vice-versa

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103
Q

What would happen if you put a p-gate in a p-substrate?

A

The source and drain would short together

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104
Q

What are other names for the bulk?

A

Back-gate, body, 4th gate

105
Q

What are other names for ptap?

A

P-substrate-tap, P-substrate-tie, P-substrate-strap, tie-down

106
Q

What are other names for the ntap?

A

nwell-tap, nwell-tie, nwell-strap, tie-up

107
Q

What is a DRC width check?

A

Minimum distance between inside edge and inside edge of same layer

108
Q

What is a DRC spacing check?

A

Minimum distance check from outside edge to another outside edge of same layer. Also applies to corner to corner check, the notch check, and the donut hole check.

109
Q

What is a fat metal rule?

A

Accounts for manufacturing difficulties as a result of the loading effect etch that can lead to issues like larger line edge roughness. Plasma etching. Line quality is better for thinner metals.

110
Q

What is an extension check?

A

Minimum distance of one layer extending beyond the edge of another layer. This is a distance check of an inside edge to an outside edge.

111
Q

What are other names for extension check?

A

Overhang check, end-cap check

112
Q

What is the enclosure check?

A

A check that one layer completely surrounds another layer by a minimum distance. Distance check of an inside edge of a layer to an outside edge of another. The layer with the outside edge must be completely inside the other layer.

113
Q

What’s an area check?

A

The minimum area check of a layer in um^2

114
Q

What’s an intersection check?

A

Minimum distance of one layer overlapping another. Inside edge to inside edge check.

115
Q

What’s another name for intersection check?

A

Overlap check.

116
Q

What does CIW stand for, and what does it do?

A

Command Interpreter Window. The first window that appears when you start Cadence. Controls the software.

117
Q

Where do Cadence messages appear?

A

In the CIW message window

118
Q

Where do messages from the current command appear?

A

In the CIW prompt line

119
Q

What is the CIW input line for?

A

Typing in SKILL functions or enter coordinates

120
Q

What does the ampersand mean in icfb&?

A

Run in background

121
Q

Where can you set up and toggle the icon menu, mouse settings line, and prompt line?

A

CIW->Options->User Preferences

122
Q

What does LSW stand for?

A

Layer and Selection Window

123
Q

What is the LSW for?

A

Chosing design layer, make objects visible or invisible, or make objects selectable or unselectable.

124
Q

How do you open the library browser?

A

CIW->tools->library browser

125
Q

What does the title bar of the cellview window display?

A

Info about the cell you’re viewing, including lib, cell, view name

126
Q

What does the status banner do?

A

Displays info about the cursor, selection, points, and command

127
Q

What do you use the cursor and pointer for?

A

Cursor to enter points or select design objects. Pointer to select menu items of options in command forms

128
Q

What does the promptline do in the Layout Cellviews window?

A

Shows instructions from the current command.

129
Q

What does the Tools menu do?

A

Lists available Cadence apps. The list differs depending on what you’ve purchased.

130
Q

What does the Design menu do?

A

Save or discard design changes, move within design hierarchy, plot a design, or set defaults.

131
Q

What does the Window menu do?

A

Change the appearance of the cellview, or change what you are viewing in this cellview.

132
Q

What does the Create menu do?

A

Draw shapes of place cell instance, devices, contacts, labels, or pins.

133
Q

What does the Edit menu do?

A

Move, copy, modify, delete or search for objects in this cellview

134
Q

What does the Verify menu do?

A

Run various verification checks on the design in this cellview

135
Q

What does the Misc menu do?

A

Perform additional editing tasks or display additional data about this cellview

136
Q

What options are in the Layout Editor popup window?

A

Instance…, Move, Copy, Delete, Properties…

137
Q

What does the Display Options form do?

A

Controls the appearance of objects and the behavior of commands in this cellview.

138
Q

How do you open the Display Options form?

A

Design->Options->Display or Type ‘e’

139
Q

What Display controls can you toggle in the Display Options window?

A

Nets, Access Edges, Instance Pins, Array Icons, Label origins, Dynamic Hilight, Tiny Inst Detail, Axes, Path borders, Instance Origins, EIP surround, Pin Names, Dot Pins

140
Q

Where can you specify the exact range of display levels?

A

Display Controls (‘e’)

141
Q

Where can you set features of the grid?

A

Display Controls (‘e’)

142
Q

What layer properies are shown in the LSW?

A

Layer stipple pattern and color, Layer name, Layer purpose

143
Q

What are common layer purposes?

A

dg = drawing (most common) wg = warning, er = errors, nt = net, t0 = tool0, t1 = tool1, etc.

144
Q

What are the four buttons in the LSW?

A

AV = All Viewable, NV = Not Viewable, AS = All Selectable, NS = Not Selectable

145
Q

How do you toggle the visibility of an individual layer in the LSW?

A

MMB

146
Q

How do you toggle an individual layer’s selectibility in the LSW?

A

RMB

147
Q

What is the Show Layers form?

A

Allows you to show / hide Instances, pins, and a few other layers and objects

148
Q

What is our Assura DRC rules file called?

A

assuraDRC.rul

149
Q

What is a reference libraray?

A

As opposed to working library. a read-only library.

150
Q

What is a cell call?

A

The operation of creating an instance.

151
Q

What is a master cell?

A

The cell an instance is linked to.

152
Q

What are the benefits of instances?

A
  1. Reuse existing cells without having to redraw them2. Instant updates when master cell is modified3. Save memory and disk space.
153
Q

What’s a mosaic?

A

A layout object which is formed by a 1 or 2-d duplication of ONE instance.

154
Q

What’s the current cell?

A

The cell that’s currently being edited.

155
Q

What’s the top cell?

A

The cell which is initially opened from a library.

156
Q

What are other names for top cell

A

Primary cell, level 0 cell

157
Q

What’s a master name?

A

Cell name as it’s used in a library

158
Q

What’s an instance name?

A

Unique name assigned to every instance. Automatically created and can be overwritten.

159
Q

What’s hard-data?

A

Objects that aren’t instances or arrays.

160
Q

What’s another name for hard data?

A

Hand-drawn objects.

161
Q

What’s another name for mosaic?

A

Array

162
Q

What’s a flat-cell?

A

Contains no instances or arrays. Nothing but hard-data.

163
Q

What are leaf-cells?

A

Misc small cells used together with big blocks

164
Q

What does descend mean?

A

Opening a master cell by going down from the parent cells through the hierarchy. One decend take you down one level at a time.

165
Q

What does edit-in-place mean?

A

Same as descend, except goes to any level instead of down only one level. Allows you to see all other levels while editing.

166
Q

What does make cell mean?

A

Push some objects one level below the current one. A new cell containing those objects will be created in your library.

167
Q

What does flatten mean?

A

Reverse of make cell. Raises objects one level up.

168
Q

What does stream out mean?

A

Converts proprietary layout data-base format to an industrial standard layout database format.

169
Q

What is stream in?

A

Converts a standard layout format to a proprietary one.

170
Q

What does Update Instances do when copying?

A

Allows resetting of references points for copied instances and arrays.

171
Q

What is the Transistor Channel Width (W)?

A

The distance between the two diffusion edges of a MOSFET active gate area

172
Q

What is the Transistor Channel Length (L)?

A

Distance between the two poly edges of a MOSFET active gate area.

173
Q

What are three common ways to show transistor (gate) sizes?

A
  1. W/L ratio - 20/0.1 means W= 20 um, L = 0.1 um2. W=, L= - W= 20 u, L = 0.1 u3. M factor - W = 5u L = 0.1u M=4 (multiplication factor)
174
Q

How do you turn on an NMOS?

A

Apply voltage (such as VDD) higher than that of the bulk. This creates an Electric Field Effect, which attracts electrons to form a channel of carriers across the N+ terminals.

175
Q

How do you turn on a PMOS?

A

Apply voltage (such as VSS) lower than that of the bulk. This creates an Electric Field Effect, which attracts holes to form a channel of carriers across the P+ terminals.

176
Q

What is the transistor (gate) strength equation?

A

Ids = (u E0 ESio2 W / Tox L) X [a function of the gate voltage]Ids = current between D & S terminalsu = surface mobility of charge carriersE0 = Permittivity of vacuumESio2 = Dielectric constant of SiO2Tox = Gate oxide thicknessW = channel widthL = channel length

177
Q

What is the surface mobility of electrons?

A

~500 cm^2 / v-sec

178
Q

What’s the surface mobility of holes?

A

~300 cm^2 / v-sec

179
Q

Why are PMOSes weaker than NMOSes?

A

Because the surface mobility (u) of holes is lower, and that’s part of the numerator in the gate strength equation.

180
Q

What is the standard permittivity value?

A

8.85 x 10-3 fF/um

181
Q

What is another name for the dielectric constant?

A

Relative Permittivity

182
Q

What’s the definition of the dielectric constant?

A

The measure of a material’s ability to resist the formation of an electric field within it, relative to a vacuum’s ability to resist the formation of an electric field.

183
Q

What’s the dielectric constant of SiO2?

A

3.9

184
Q

What size is the gate oxide thickness?

A

~200 angstroms

185
Q

How do W and L relate to a gate’s strength?

A

The larger the W, the stronger the gate. The smaller the L, the stronger the gate.

186
Q

What’s a finger gate?

A

A transistor that’s been split into multiple segments (or fingers) and these segments are the reconnected back together to form the required W/L ratio.

187
Q

What are other names for finger gates?

A

Interdigitated gates, Split Gates, Folding Gates, Legged Gates.

188
Q

Beneftis of finger gates:

A
  1. Fit into specific areas2. Speed improvement due to reduced total diffusion areas (reduced capacitance) and due to reduced resistance because of the shortening of poly lines.3. Mandatory in many matching transistor layouts.
189
Q

What is the only correct way to layout finger gates in series in Analog circuits?

A

Split each mosfet individually and connect those groups in series.

190
Q

What technology are we using in school?

A

.1um 5 layer metal BiCMOS nwell process

191
Q

How do proton and neutron masses relate?

A

Almost the same

192
Q

How do electron and proton charges relate?

A

Almost same charge, with reversed polarity

193
Q

What are other names for device terminals?

A

Legs, pins, leads

194
Q

What is another name for devices?

A

Discrete components

195
Q

What are examples of good conductors?

A

Copper, Aluminum, Gold, Silver

196
Q

What are examples of poor conductors?

A

Plastic, wood, air, silicon dioxide SiO2, silicon nitride (Si3N4)

197
Q

What’s poly short for?

A

Polycrystalline silicon

198
Q

How many valence electrons does silicon have?

A

4

199
Q

How many valence electrons does boron have?

A

3

200
Q

How many valence electrons does arsenic have?

A

5

201
Q

How many atoms does pure silicon have?

A

5x10^22 per cm^3

202
Q

What do N, N+, and N- mean?

A

silicon doped with arscenic, N = moderate, N+ = very high, N- = very light

203
Q

What are the silicon-related layers (base layers)?

A

p-substrate, nwell, diffusions, oxide, poly

204
Q

When can you share diffusion?

A

Same node name, same material type

205
Q

Who builds the actual masks?

A

Mask vendor / mask shop

206
Q

What is the symbol for charges?

A

Q

207
Q

What is the unit of measurement of charges?

A

coulombs (C)

208
Q

What is the definition of charges?

A

Amount of electricity

209
Q

What’s the definition of voltage?

A

Difference in potential

210
Q

What is the symbol for voltage?

A

V

211
Q

What are other names for voltage difference?

A

potential difference, electro-motive force (emf)

212
Q

What is the symbol for electrical current?

A

I

213
Q

What is electrical current?

A

Charges moving along a conductor

214
Q

What is the unit of measurement for current?

A

Amperes (A), which is number of coulumbs per second

215
Q

What determines which way current flows?

A

Always from higher to lower voltage.

216
Q

What are the ends of a diode called?

A

anode (p side), cathode (n side)

217
Q

What are majority and minority carriers?

A

p-material, holes are the majority, n-material, electrons are the majority

218
Q

Steps to connect an nwell to certain potential

A
  1. Draw at least one piece of ndiff inside the nwell2. Draw at least one contact on each ndiff3. Draw piece of m1 covering that contact.4. Connect m1 to correct node name.
219
Q

Guidelines for laying out taps (5 items)

A
  1. More taps the better if time and space is available.2.More contacts on each tap the better if time and space is available.3. Each device is required to see a tap within 5 um.4. Taps closer to the divide the better.5. Best location is between pmos and nmos. Increases isolation / separation bewteen nwell and p-substrate. Thicker depletion layer.
220
Q

What is a guard ring?

A

Lots of taps around a device

221
Q

Why the spacing rules?

A

Overcome misalignment errors

222
Q

Define pitch

A

Minimum width + minimum spacing.

223
Q

What percentage of layers are drawn layers?

A

About 2/3. 1/3 generated layers / CAD layers.

224
Q

What is the general name for companies like Cadence?

A

EDA - Electronic Design Automation company

225
Q

How much does virtuoso cost?

A

$30k per seat / $80k advanced

226
Q

What does DFII stand for?

A

Design Framework II

227
Q

What are the files called that come from the manufacturer?

A

Tech files, technology files

228
Q

What does PDK stand for?

A

Process Design Kit

229
Q

What is the extension of the file to compile when creating a new library?

A

.tf

230
Q

What is the off grid issue?

A

When diagonal lines or circles cause vertices to not line up with the grid

231
Q

What is the panic file?

A

In case of power loss, etc, can be recovered from command line.

232
Q

What are the five ways to enter a command in the layout editor?

A

MenuOn-screen iconsBind KeyStroke Gesturecommand line

233
Q

What is the reference point?

A

Shows last click

234
Q

What is the INFIX option?

A

When on, no click is necessary for first point

235
Q

Where is the INFIX option?

A

CIW->Options->user preferences

236
Q

What is window stretch

A

Stretching two or more edges.

237
Q

What does PDV stand for?

A

Physical Design Verification

238
Q

What does DRC stand for?

A

Design Rule Check

239
Q

What are other names for the DRC rule files?

A

rule set, rule deck, command files

240
Q

What are examples of DRC programs?

A

Assura, Diva, Dracula

241
Q

How do you run DRC?

A

Layout editor->Assura->Run DRC…

242
Q

What are issues when drawing polygons?

A

re-entrant issue, self-intersecting issue, no acute angles

243
Q

What are chopped corners called?

A

chamfers

244
Q

What are the three big EDA companies?

A

Cadence, Mentor, Synopsys

245
Q

What are smaller EDA companies?

A

Tanner - ledit / Springsoft - Laker

246
Q

What does LVS stand for?

A

Layout Versus Schematic

247
Q

What are the two standard layout formats?

A

GDS and CIF

248
Q

What does GDS stand for?

A

Graphical Display Screen (the most common standard layout format)

249
Q

What does CIF stand for?

A

Caltech Intermediate Form, the newer (but less common) layout format

250
Q

Who made the first layout machine?

A

Calma Design Systems

251
Q

When is it appropriate to use stream in / out instead of import / export?

A

With GDS files. CIF files you should use import / export

252
Q

What are alternate names for GDS files?

A

stream files, calma files

253
Q

What are common file extensions for GDS files?

A

.gds .sf .gds2 .st

254
Q

What are three things you need to set when streaming out?

A
  1. Which layout2. GDS filename3. Layer map file (sdi_stream.map)
255
Q

What are two common warnings after streaming out?

A

Layer not being exported, lables translated on stream font 0

256
Q

What are things you need to set up when streaming in?

A
  1. Where and name of GDS file2. Name of library3. Top cell name4. Layer map file (sdi_stream.map)
257
Q

What’s another name for the active gate area?

A

transistor area

258
Q

What does surface inversion mean, and when is a mosfet working in inversion mode?

A

Surface inversion is when the material between source and drain becomes a conductive channel - N- becomes P+, or P- becomes N+ So a mosfet is working in inversion mode when it’s on.

259
Q

What is PIPO.LOG for?

A

Logs all statistical information about stream-out or stream-in operation. Also contains info about warnings and errors.

Layout (24 decks)

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