Lecture 8

Question 1

VHDL data types: BOOLEAN

Answer 1

Returned by comparisons and used in conditional statements

True and false

Y <= d1 when (s=‘1st) else d0;

Question 2

VHDL data types: INTEGER

Answer 2

Represents both positive and negative integers

-2^31 to (2^31)-1

Y <= a(3) and a(2) and a(1) and a(0);

Question 3

CONV_INTEGER

Answer 3

Converts from STD_LOGIC_VECTOR to INTEGER for positive (unsigned) values

Defined in library IEEE.STD_LOGIC_UNSIGNED

Y <= d(CONV_INTEGER(s));

Question 4

VHDL is strict about out port being exclusively for output

Answer 4

Has a buffer port type that solves this

Question 5

Buffer port

Answer 5

Signals behave as outputs but may alone be used within the module

Question 6

Enumeration

Answer 6

An abstract way of representing information without assigning specific binary encodings

Question 7

Structural modeling

Answer 7

Describes a module in terms of how it is composed of simpler modules

Prevents errors caused by changing the entity but not the instance

Allows multiple architectures (implementations) for the same entity

Question 8

VHDL process statements

Answer 8

Used to describe sequential circuits because they remember the old state when no new state prescribed

Can be used to describe combinatorial logic

Question 9

Process statements can be used to describe combinatorial logic if:

Answer 9

The sensitivity list is written to respond to changes in all of the inputs

The body prescribes the output value for every possible input combination

Question 10

Process statement: <=

Answer 10

Non-blocking assignment

Question 11

Non-blocking assignment

Answer 11

Evaluated concurrently before any of the signals on left side are updates

Made to outputs and to signals

Question 12

Process statements: :=

Answer 12

Blocking assignment

Question 13

Blocking assignment

Answer 13

Evaluated in order that they appear in the code

Made to variables

Best for intermediate variables in combinatorial logic (must be variable not signal)

Question 14

Case statements

Answer 14

Checks the value of data

Must appear within always statement

Question 15

(Non-)Blocking Assignment Guidelines

Answer 15

1. Use process (clk) and nonblocking assignments to model synchronous sequential logic
2. Use concurrent assignments outside process statements to model simple combinatorial logic
3. Use process (in1,in2,…) and blocking assignments to model more complicated combinatorial logic
4. Do not make assignments to the same signal in more than one process statement or concurrent assignment statement