Final

Question 1

Maximum time from when an input changes until outputs reach their final value

Answer 1

Propagation delay tpd

Question 2

Minimum time from when an input changes until any output starts to change value

Answer 2

Contamination delay tcd

Question 3

Longest and slowest path in a circuit

Answer 3

Critical path

Question 4

Shortest and fastest path through the circuit

Answer 4

Short path

Question 5

When a single input transition causes multiple output transitions

Answer 5

Glitches/hazards

Question 6

Contain all information about the past necessary to explain future circuit behavior

Answer 6

State variables

Question 7

Having 2 stable states

Answer 7

Bistable

Question 8

State of the circuit if both outputs were between 0 and 1

Answer 8

Metastable

Question 9

State of a latch in which data is blocked from flowing through to output, so output retains its old value

Answer 9

Opaque

Question 10

State of a latch in which data flows through to output as if it were just a buffer

Answer 10

Transparent

Question 11

A pair of back-to-back latches controlled by complementary clocks

Answer 11

Flip-flop

Question 12

A bank of N flip-flops that share a common clock input

Answer 12

Register

Question 13

Containing a control input that causes a circuit to retain its state when FALSE

Answer 13

Enabled

Question 14

A type of circuit whose output cannot be determined simply by looking at the current inputs

Answer 14

Sequential

Question 15

Updating based on a clock input, whose rising edges indicate a sequence of times at which state transitions occur

Answer 15

Synchronous

Question 16

A type of circuit with no stable states (ring oscillator)

Answer 16

Astable

Question 17

A characteristic where the output of a circuit depends on the delays through certain gates, often causing it to fail when some gates slower than others

Answer 17

Race conditions

Question 18

Loops in which outputs are fed directly back to inputs

Answer 18

Cyclic paths

Question 19

Details next state and value of each output for each possible combination of current state and input values

Answer 19

Functional specification

Question 20

An HDL module used to test another module

Answer 20

Testbench

Question 21

The module tested by a testbench

Answer 21

Device/Unit Under Test (DUT/UUT)

Question 22

Occurring immediately, without waiting for next clock cycle

Answer 22

Asynchronous

Question 23

A synchronous sequential circuit with k registers that can be in one of a finite number of states

Answer 23

Finite State Machine (FSM)

Question 24

A class of FSMs where outputs depend only on current state of machine

Answer 24

Moore machine

Question 25

A class of FSMs where outputs depend on both current state of machine and current inputs

Answer 25

Mealy machine

Question 26

Breaking down a complex FSM into multiple interacting state machines; an application of hierarchy and modularity

Answer 26

Factoring

Question 27

Implies that all values in the system are fully represented by a series of digits

Answer 27

Digital

Question 28

Of or relating to a mechanism that represents data by measurement of a continuous physical variable, as voltage or pressure

Answer 28

Analog

Question 29

Hiding details when they are not important

Answer 29

Abstraction

Question 30

Intentionally restricting your design choices so that you can work more productively at a higher level of abstraction

Answer 30

Discipline

Question 31

Dividing a system into modules, then further subdividing each of these modules until the pieces are easy to understand

Answer 31

Hierarchy

Question 32

Giving modules well-defines functions and interfaces, so that they connect together easily without side effects

Answer 32

Modularity

Question 33

Ensuring uniformity among modules can be reused many times

Answer 33

Regularity

Question 34

Multiplexer delays: control inputs arrive before data

Answer 34

Choose hierarchical design - shortest control to output delay

Question 35

Multiplexer delay: data inputs arrive before control

Answer 35

Choose tristate design - shortest data to output delay

Question 36

Ripple-carry adder

Answer 36

Simplest way to build N-bit CPA Chains together N full adder Cout of one stage acts as Cin of the next stage Application of modularity and regularity

Question 37

Ripple-carry adder: disadvantage

Answer 37

Slow when N is large Carry ripples through the carry chain Delay of adder grows directly with N

Question 38

Carry look ahead adder

Answer 38

Generate and propagate signals for block spanning columns i to j Block generates carry if most significant column generates carry or most significant column propagates carry Block propagates carry if all columns in block propagate carry Each block contains 4-bit RCA and lookahead Logic to compute carry out of block given the carry in And and or gates needed to compute single-but generate and propagate signals

Question 39

Prefix adder

Answer 39

Begins with a precomputation to form P and G for each column from A and B using AND and OR gates

Question 40

Shifter

Answer 40

Shifts a binary number left or right by a set of # of positions

Question 41

Logical shifter

Answer 41

Shifts number to the left (LSL) or right (LSR) and fills empty spots with zeros

Question 42

Arithmetic shifter

Answer 42

On right shifts, fills most significant bits with a copy of the old most significant bits (ASL=LSL)

Question 43

Rotator

Answer 43

Rotates in a circle such that empty spots are filled with bits shifter off the other end

Question 44

An N bit shifter can be built from

Answer 44

N N-by-1 Muxes