Final Flashcards
Maximum time from when an input changes until outputs reach their final value
Propagation delay tpd
Minimum time from when an input changes until any output starts to change value
Contamination delay tcd
Longest and slowest path in a circuit
Critical path
Shortest and fastest path through the circuit
Short path
When a single input transition causes multiple output transitions
Glitches/hazards
Contain all information about the past necessary to explain future circuit behavior
State variables
Having 2 stable states
Bistable
State of the circuit if both outputs were between 0 and 1
Metastable
State of a latch in which data is blocked from flowing through to output, so output retains its old value
Opaque
State of a latch in which data flows through to output as if it were just a buffer
Transparent
A pair of back-to-back latches controlled by complementary clocks
Flip-flop
A bank of N flip-flops that share a common clock input
Register
Containing a control input that causes a circuit to retain its state when FALSE
Enabled
A type of circuit whose output cannot be determined simply by looking at the current inputs
Sequential
Updating based on a clock input, whose rising edges indicate a sequence of times at which state transitions occur
Synchronous
A type of circuit with no stable states (ring oscillator)
Astable
A characteristic where the output of a circuit depends on the delays through certain gates, often causing it to fail when some gates slower than others
Race conditions
Loops in which outputs are fed directly back to inputs
Cyclic paths
Details next state and value of each output for each possible combination of current state and input values
Functional specification
An HDL module used to test another module
Testbench
The module tested by a testbench
Device/Unit Under Test (DUT/UUT)
Occurring immediately, without waiting for next clock cycle
Asynchronous
A synchronous sequential circuit with k registers that can be in one of a finite number of states
Finite State Machine (FSM)
A class of FSMs where outputs depend only on current state of machine
Moore machine
A class of FSMs where outputs depend on both current state of machine and current inputs
Mealy machine
Breaking down a complex FSM into multiple interacting state machines; an application of hierarchy and modularity
Factoring
Implies that all values in the system are fully represented by a series of digits
Digital
Of or relating to a mechanism that represents data by measurement of a continuous physical variable, as voltage or pressure
Analog
Hiding details when they are not important
Abstraction
Intentionally restricting your design choices so that you can work more productively at a higher level of abstraction
Discipline
Dividing a system into modules, then further subdividing each of these modules until the pieces are easy to understand
Hierarchy
Giving modules well-defines functions and interfaces, so that they connect together easily without side effects
Modularity
Ensuring uniformity among modules can be reused many times
Regularity
Multiplexer delays: control inputs arrive before data
Choose hierarchical design - shortest control to output delay
Multiplexer delay: data inputs arrive before control
Choose tristate design - shortest data to output delay
Ripple-carry adder
Simplest way to build N-bit CPA
Chains together N full adder
Cout of one stage acts as Cin of the next stage
Application of modularity and regularity
Ripple-carry adder: disadvantage
Slow when N is large
Carry ripples through the carry chain
Delay of adder grows directly with N
Carry look ahead adder
Generate and propagate signals for block spanning columns i to j
Block generates carry if most significant column generates carry or most significant column propagates carry
Block propagates carry if all columns in block propagate carry
Each block contains 4-bit RCA and lookahead Logic to compute carry out of block given the carry in
And and or gates needed to compute single-but generate and propagate signals
Prefix adder
Begins with a precomputation to form P and G for each column from A and B using AND and OR gates
Shifter
Shifts a binary number left or right by a set of # of positions
Logical shifter
Shifts number to the left (LSL) or right (LSR) and fills empty spots with zeros
Arithmetic shifter
On right shifts, fills most significant bits with a copy of the old most significant bits (ASL=LSL)
Rotator
Rotates in a circle such that empty spots are filled with bits shifter off the other end
An N bit shifter can be built from
N N-by-1 Muxes
