Final Flashcards

1
Q

Maximum time from when an input changes until outputs reach their final value

A

Propagation delay tpd

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2
Q

Minimum time from when an input changes until any output starts to change value

A

Contamination delay tcd

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3
Q

Longest and slowest path in a circuit

A

Critical path

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4
Q

Shortest and fastest path through the circuit

A

Short path

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5
Q

When a single input transition causes multiple output transitions

A

Glitches/hazards

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6
Q

Contain all information about the past necessary to explain future circuit behavior

A

State variables

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7
Q

Having 2 stable states

A

Bistable

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8
Q

State of the circuit if both outputs were between 0 and 1

A

Metastable

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9
Q

State of a latch in which data is blocked from flowing through to output, so output retains its old value

A

Opaque

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10
Q

State of a latch in which data flows through to output as if it were just a buffer

A

Transparent

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11
Q

A pair of back-to-back latches controlled by complementary clocks

A

Flip-flop

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12
Q

A bank of N flip-flops that share a common clock input

A

Register

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13
Q

Containing a control input that causes a circuit to retain its state when FALSE

A

Enabled

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14
Q

A type of circuit whose output cannot be determined simply by looking at the current inputs

A

Sequential

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15
Q

Updating based on a clock input, whose rising edges indicate a sequence of times at which state transitions occur

A

Synchronous

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16
Q

A type of circuit with no stable states (ring oscillator)

A

Astable

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17
Q

A characteristic where the output of a circuit depends on the delays through certain gates, often causing it to fail when some gates slower than others

A

Race conditions

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18
Q

Loops in which outputs are fed directly back to inputs

A

Cyclic paths

19
Q

Details next state and value of each output for each possible combination of current state and input values

A

Functional specification

20
Q

An HDL module used to test another module

A

Testbench

21
Q

The module tested by a testbench

A

Device/Unit Under Test (DUT/UUT)

22
Q

Occurring immediately, without waiting for next clock cycle

A

Asynchronous

23
Q

A synchronous sequential circuit with k registers that can be in one of a finite number of states

A

Finite State Machine (FSM)

24
Q

A class of FSMs where outputs depend only on current state of machine

A

Moore machine

25
Q

A class of FSMs where outputs depend on both current state of machine and current inputs

A

Mealy machine

26
Q

Breaking down a complex FSM into multiple interacting state machines; an application of hierarchy and modularity

A

Factoring

27
Q

Implies that all values in the system are fully represented by a series of digits

A

Digital

28
Q

Of or relating to a mechanism that represents data by measurement of a continuous physical variable, as voltage or pressure

A

Analog

29
Q

Hiding details when they are not important

A

Abstraction

30
Q

Intentionally restricting your design choices so that you can work more productively at a higher level of abstraction

A

Discipline

31
Q

Dividing a system into modules, then further subdividing each of these modules until the pieces are easy to understand

A

Hierarchy

32
Q

Giving modules well-defines functions and interfaces, so that they connect together easily without side effects

A

Modularity

33
Q

Ensuring uniformity among modules can be reused many times

A

Regularity

34
Q

Multiplexer delays: control inputs arrive before data

A

Choose hierarchical design - shortest control to output delay

35
Q

Multiplexer delay: data inputs arrive before control

A

Choose tristate design - shortest data to output delay

36
Q

Ripple-carry adder

A

Simplest way to build N-bit CPA

Chains together N full adder

Cout of one stage acts as Cin of the next stage

Application of modularity and regularity

37
Q

Ripple-carry adder: disadvantage

A

Slow when N is large

Carry ripples through the carry chain

Delay of adder grows directly with N

38
Q

Carry look ahead adder

A

Generate and propagate signals for block spanning columns i to j

Block generates carry if most significant column generates carry or most significant column propagates carry

Block propagates carry if all columns in block propagate carry

Each block contains 4-bit RCA and lookahead Logic to compute carry out of block given the carry in

And and or gates needed to compute single-but generate and propagate signals

39
Q

Prefix adder

A

Begins with a precomputation to form P and G for each column from A and B using AND and OR gates

40
Q

Shifter

A

Shifts a binary number left or right by a set of # of positions

41
Q

Logical shifter

A

Shifts number to the left (LSL) or right (LSR) and fills empty spots with zeros

42
Q

Arithmetic shifter

A

On right shifts, fills most significant bits with a copy of the old most significant bits (ASL=LSL)

43
Q

Rotator

A

Rotates in a circle such that empty spots are filled with bits shifter off the other end

44
Q

An N bit shifter can be built from

A

N N-by-1 Muxes