Lecture 6 Flashcards
reduction operators
Imply a multiple input gate acting on a single bus
VHDL does not have these
Can write an and8 module explicitly using your own entity and architecture statements
Provides the generate command to produce a variable amount of hardware depending on the value of a parameter
Conditional assignments
Select output from among alternatives based on an input called the condition
Useful for describing a multiplexer (MUX)
2:1 MUX
Can use conditional signal assignment to select one of two 4-bit inputs
- sets y to d0 if s is 0
- otherwise, sets y to d1
Selected signal assignment statements
Provides a short hard when selecting from one of several possibilities
Case statement in place of multiple if/else statements
With a select y <=
… when others;
Full adder
S = A xor B xor Cin Court = AB+ACin+BCin
Intermediate signals:
- P = A xor B
- G = AB
Full adder with intermediate signals
S = P xor Cin Court = G+PCin
Internal variables
Neither inputs nor outputs but are used only internal to the module
Similar to local variables in programming
HDL assignment statements
Take place concurrently
Order does not matter
Are evaluated any time the inputs (signals on the right hand side) change their value regardless or order
VHDL signals
Used to represent internal variables whose values are defined by concurrent signal assign statements
VHDL Precedence
Highest:
Not
*, /, mod, rem
+, -, &
Lowest:
Rol, ror, srl, sll, sra, sla
=, /=, , >=
And, or, nand, nor, xor
In VHDL, STD_LOGIC numbers are written in
Binary and enclosed in single quotes: ‘0’ and ‘1’
STD_LOGIC_VECTOR numbers
Binary or hexadecimal
Double quotation marks
“101”
3 bits
Base 2
Val = 5
Stored - 101
B”101”
3 bits
Base 2
Val = 3
Stored - 101
X”AB”
Bits - 8
Base 16
Val = 161
Stored - 10101011
HDL’s use Z to indicate a
Floating value (high impedance)
Tri-state buffer
Output floats when the enable is 0
If the buffer is enabled
The output is the same as the input
If the buffer is disabled
The output is assigned a floating value (z)
HDLs use X to indicate
An invalid logic level
VHDL uses u to indicate
An unknown state
U’s
Helpful to track errors caused by forgetting to reset
At start of simulation, state nodes such as flip-flop outputs are initialized to an unknown state
‘S
If a bus is simultaneously driven to 0 and 1 by 2 enabled tristate buffers, the result is x
If a gate receives a floating input, it may produce an x output if it can’t determine the correct output value
Seeing X or U values in simulation is usually an indication of
A bug or bad coding practice
VHDL delays
The after clause
Helpful during simulation to predict how fast a circuit will work
Use for debugging purposes to understand cause and effect
Ignored during synthesis
Logical simulation
Tests a system on a computer before it is turned into HW
Logical synthesis
Converts HDL code into digital logic circuits
Schematic
A diagram of a digital circuit showing the elements and wires that connect them together
