Lecture 3 Flashcards
Leading HDLs
Verilog and VHDL (VHSIC HDL)
VHSIC HDL
Very high speed integrate circuits
DoD program
Verilog
Developed by Gateway Design Automation as a propriety language for logic simulation in 1984
IEEE Standard in 1995
VHDL
Developed in 1981 by DoD to describe the structure and function of HW
Roots draw from Ada programming language
IEEE Standard in 1987
Language first envisioned for documentation, but adopted for simulation and synthesis
Module
Block of hardware with inputs and outputs
AND gate, multiplexer, priority circuit
Describing module functionality
Behavioral, structural
Behavioral modeling
Models that describe what a module does
Structural modeling
Describe how module built from different pieces; application of hierarchy
VHDL code has 3 parts
The library use clause, the entity declaration, and the architecture body
Library use clause
IEEE.STD_LOGIC_1164 defines the STD_LOGIC type
library IEEE; use IEEE.STD_LOGIC_1164.all;
Entity declaration
Lists the module name and its inputs and outputs
entity myfunction is
…
end;
Architecture body
Defines what the modules does
architecture synth of myfunction is
begin
…
end;
VHDL signals
Inputs and outputs
Must have a type declaration
Digital signals should be declared to be STD_LOGIC type, values of 0, 1, Z, X
Major purposes of HDLs
Logic simulation and synthesis
Simulation
Inputs are applied to a module, and outputs are checked to verify that the module operates correctly
To catch bugs because people routinely make mistakes
Synthesis
The textual description of a module is transformed into logic gates
Transforms HDL code into a netlist describing HW (the logic gates and the wires connecting them)
Since building HW is primary goals, emphasize a ______ of the VHDL language
Synthesizable subset - divide HDL code into synthesizable modules and a testbench
Synthesizable modules
Describe HW
Testbench
Contains code to apply inputs to a module, check whether output results correct, and print discrepancies between expected and actual outputs
Intended for simulation only and cannot be synthesized
HDLs have ___
Idioms
Idioms
Specific ways of describing various classes of logic
Combinational logic
Synchronous sequential circuits consist of combinatorial logic and registers
Outputs of combinatorial logic depend only on the current inputs
Bit wise operator
Acts on single-bit signals or on multi-bit busses
4-but bus
STD_LOGIC_VECTOR (3 downto 0)
Msb to lsb—> a[3], a[2], a[1], and a[0]
Little endian order
Least significant bit has smallest bit number
MSB to LSB
Big endian order
LSB to MSB
VHDL operators
Not, xor, or
Operands
A,b,y1
Expression
Combination of operators and operands (a nor b)
Statement
Complement command (y4 <= a nand b);)
Concurrent signal assignment statement
Describes combinational logic, ends with a semicolon (out <= in1 op in2;)
VHDL comments
Begin with - - and continue to the end of the line
module and signal names must not begin with a ____
Digit
