Lecture 3

Question 1

Leading HDLs

Answer 1

Verilog and VHDL (VHSIC HDL)

Question 2

VHSIC HDL

Answer 2

Very high speed integrate circuits

DoD program

Question 3

Verilog

Answer 3

Developed by Gateway Design Automation as a propriety language for logic simulation in 1984

IEEE Standard in 1995

Question 4

VHDL

Answer 4

Developed in 1981 by DoD to describe the structure and function of HW

Roots draw from Ada programming language

IEEE Standard in 1987

Language first envisioned for documentation, but adopted for simulation and synthesis

Question 5

Module

Answer 5

Block of hardware with inputs and outputs

AND gate, multiplexer, priority circuit

Question 6

Describing module functionality

Answer 6

Behavioral, structural

Question 7

Behavioral modeling

Answer 7

Models that describe what a module does

Question 8

Structural modeling

Answer 8

Describe how module built from different pieces; application of hierarchy

Question 9

VHDL code has 3 parts

Answer 9

The library use clause, the entity declaration, and the architecture body

Question 10

Library use clause

Answer 10

IEEE.STD_LOGIC_1164 defines the STD_LOGIC type

library IEEE; use IEEE.STD_LOGIC_1164.all;

Question 11

Entity declaration

Answer 11

Lists the module name and its inputs and outputs

entity myfunction is
…
end;

Question 12

Architecture body

Answer 12

Defines what the modules does

architecture synth of myfunction is
begin
…
end;

Question 13

VHDL signals

Answer 13

Inputs and outputs

Must have a type declaration

Digital signals should be declared to be STD_LOGIC type, values of 0, 1, Z, X

Question 14

Major purposes of HDLs

Answer 14

Logic simulation and synthesis

Question 15

Simulation

Answer 15

Inputs are applied to a module, and outputs are checked to verify that the module operates correctly

To catch bugs because people routinely make mistakes

Question 16

Synthesis

Answer 16

The textual description of a module is transformed into logic gates

Transforms HDL code into a netlist describing HW (the logic gates and the wires connecting them)

Question 17

Since building HW is primary goals, emphasize a ______ of the VHDL language

Answer 17

Synthesizable subset - divide HDL code into synthesizable modules and a testbench

Question 18

Synthesizable modules

Answer 18

Describe HW

Question 19

Testbench

Answer 19

Contains code to apply inputs to a module, check whether output results correct, and print discrepancies between expected and actual outputs

Intended for simulation only and cannot be synthesized

Question 20

HDLs have ___

Answer 20

Idioms

Question 21

Idioms

Answer 21

Specific ways of describing various classes of logic

Question 22

Combinational logic

Answer 22

Synchronous sequential circuits consist of combinatorial logic and registers

Outputs of combinatorial logic depend only on the current inputs

Question 23

Bit wise operator

Answer 23

Acts on single-bit signals or on multi-bit busses

Question 24

4-but bus

Answer 24

STD_LOGIC_VECTOR (3 downto 0)

Msb to lsb—> a[3], a[2], a[1], and a[0]

Question 25

Little endian order

Answer 25

Least significant bit has smallest bit number

MSB to LSB

Question 26

Big endian order

Answer 26

LSB to MSB

Question 27

VHDL operators

Answer 27

Not, xor, or

Question 28

Operands

Answer 28

A,b,y1

Question 29

Expression

Answer 29

Combination of operators and operands (a nor b)

Question 30

Statement

Answer 30

Complement command (y4 <= a nand b);)

Question 31

Concurrent signal assignment statement

Answer 31

Describes combinational logic, ends with a semicolon (out <= in1 op in2;)

Question 32

VHDL comments

Answer 32

Begin with - - and continue to the end of the line

Question 33

module and signal names must not begin with a ____

Answer 33

Digit