Lecture 10 Flashcards
Decoder
N inputs, 2^N outputs
Outputs are called one-hot because exactly 1 output is “hot” (HIGH) at a given time
Each output represents a single minterm, function is built as the OR of all minterms
N:2^N decoder can be constructed from 2^N N-input AND gates
Timing
Making a circuit run fast
Delay
An output takes time to change in response to an input change
Timing diagram
Portrays the transient response of the buffer circuit when input changes
Combinational logic is characterized by these 2 delays
Propagation delay, tpd
Contamination delay, tcd
Propagation delay
Maximum time from when an input changes until the outputs reach their final value
Contamination delay
Minimum time from when a input changes until any output starts to change value
A is initially either HIGH or LOW, changes to other state at particular time
Interested only in the fact that it changes
In response, Y changes some time later
Arcs indicate that Y may start to change tcd after A transitions and Y settles within tpd
Underlying causes for delay in circuits:
Time requirement to charge capacitance
The speed of light in a medium
Tpd and Tcd are different due to:
Different rising and falling delays
Multiple inputs and outputs
Circuits slowing down when hot, and speeding up when cold
Tpd and Tcd also determined by…
Path signal takes from input to output
Critical path
Longest and slowest path in a circuit
Limits the speed at which the circuit can operate
How many gates does it travel through?
Short path
Shortest and fastest path through the circuit
Propagation delay =
Function of critical path
Tpd is sum of propagation delays through each element on critical path
Contamination delay =
Function of short path
Tcd is sum of contamination delays through each element on short path
Multiplexer timing
If tpd_sy > tpd_dy, circuit is control critical
If tpd_dy > tpd_sy, circuit is data critical
If control inputs arrive before data, choose ______
Hierarchical design because shortest control-to-output delay (3 2:1 muxes)
If data inputs arrive before control, choose ________
Tristate design because shortest data-to-output delay
Glitches or hazards
Are when a single input transition causes multiple output transitions
If we wait on propagation delay before we depend on output, not a problem
Can avoid glitch by adding another gate (redundant implicant) to implementation (can output 1 throughout the transition)
Occur when a variable change crosses boundary between 2 prime implicant in a K-map
Sequential logic
Output values depend on both current and prior input values
Has memory
May explicitly remember previous inputs, or distill them into a smaller amount of system state information
State variables
Contain all information about the past necessary to explain future circuit behavior
To store one bit of state, we can use
Latches or flip-flops
Using _____, we can simplify design by building synchronous sequential circuits consisting of combinational logic and banks of flip-flops containing state of circuit
Discipline
Bistable element
2 stable states
Fundamental building block of memory
0 inputs, 2 outputs (Q and Qbar)
Cyclic
Stores 1 bit of information
Cross-coupled
I1’s inputs is I2’s outputs and vice versa
Stable
Consistent with original assumption
Metastable state
If both outputs were between 0 and 1
An element with N stable states conveys
Log2(N) bits of information
State of cross-couple inverters is contained in
1 binary state variable Q
Cross-coupled inverters
Impractical because user has no inputs to control state
SR Latch
Composed of 2 cross-coupled NOR gates
2 inputs, S & R; 2 outputs, Q and Qbar
S sets and R resets the output, Q
