Lecture 10

Question 1

Decoder

Answer 1

N inputs, 2^N outputs

Outputs are called one-hot because exactly 1 output is “hot” (HIGH) at a given time

Each output represents a single minterm, function is built as the OR of all minterms

N:2^N decoder can be constructed from 2^N N-input AND gates

Question 2

Timing

Answer 2

Making a circuit run fast

Question 3

Delay

Answer 3

An output takes time to change in response to an input change

Question 4

Timing diagram

Answer 4

Portrays the transient response of the buffer circuit when input changes

Question 5

Combinational logic is characterized by these 2 delays

Answer 5

Propagation delay, tpd

Contamination delay, tcd

Question 6

Propagation delay

Answer 6

Maximum time from when an input changes until the outputs reach their final value

Question 7

Contamination delay

Answer 7

Minimum time from when a input changes until any output starts to change value

Question 8

A is initially either HIGH or LOW, changes to other state at particular time

Answer 8

Interested only in the fact that it changes

In response, Y changes some time later

Arcs indicate that Y may start to change tcd after A transitions and Y settles within tpd

Question 9

Underlying causes for delay in circuits:

Answer 9

Time requirement to charge capacitance

The speed of light in a medium

Question 10

Tpd and Tcd are different due to:

Answer 10

Different rising and falling delays

Multiple inputs and outputs

Circuits slowing down when hot, and speeding up when cold

Question 11

Tpd and Tcd also determined by…

Answer 11

Path signal takes from input to output

Question 12

Critical path

Answer 12

Longest and slowest path in a circuit

Limits the speed at which the circuit can operate

How many gates does it travel through?

Question 13

Short path

Answer 13

Shortest and fastest path through the circuit

Question 14

Propagation delay =

Answer 14

Function of critical path

Tpd is sum of propagation delays through each element on critical path

Question 15

Contamination delay =

Answer 15

Function of short path

Tcd is sum of contamination delays through each element on short path

Question 16

Multiplexer timing

Answer 16

If tpd_sy > tpd_dy, circuit is control critical

If tpd_dy > tpd_sy, circuit is data critical

Question 17

If control inputs arrive before data, choose ______

Answer 17

Hierarchical design because shortest control-to-output delay (3 2:1 muxes)

Question 18

If data inputs arrive before control, choose ________

Answer 18

Tristate design because shortest data-to-output delay

Question 19

Glitches or hazards

Answer 19

Are when a single input transition causes multiple output transitions

If we wait on propagation delay before we depend on output, not a problem

Can avoid glitch by adding another gate (redundant implicant) to implementation (can output 1 throughout the transition)

Occur when a variable change crosses boundary between 2 prime implicant in a K-map

Question 20

Sequential logic

Answer 20

Output values depend on both current and prior input values

Has memory

May explicitly remember previous inputs, or distill them into a smaller amount of system state information

Question 21

State variables

Answer 21

Contain all information about the past necessary to explain future circuit behavior

Question 22

To store one bit of state, we can use

Answer 22

Latches or flip-flops

Question 23

Using _____, we can simplify design by building synchronous sequential circuits consisting of combinational logic and banks of flip-flops containing state of circuit

Answer 23

Discipline

Question 24

Bistable element

Answer 24

2 stable states

Fundamental building block of memory

0 inputs, 2 outputs (Q and Qbar)

Cyclic

Stores 1 bit of information

Question 25

Cross-coupled

Answer 25

I1’s inputs is I2’s outputs and vice versa

Question 26

Stable

Answer 26

Consistent with original assumption

Question 27

Metastable state

Answer 27

If both outputs were between 0 and 1

Question 28

An element with N stable states conveys

Answer 28

Log2(N) bits of information

Question 29

State of cross-couple inverters is contained in

Answer 29

1 binary state variable Q

Question 30

Cross-coupled inverters

Answer 30

Impractical because user has no inputs to control state

Question 31

SR Latch

Answer 31

Composed of 2 cross-coupled NOR gates

2 inputs, S & R; 2 outputs, Q and Qbar

S sets and R resets the output, Q