Latches and Flip-Flops Flashcards
Digital circuits can be classified in two categories. The difference between the two is the way that they produce outputs.
- _______ circuits produce outputs only when an input is applied. They are composed of logic gates that have no feedback from output to input. When the input is removed, the output stops. As a result, cthese circuits cannot store information.
- ________ circuits also produce an output when an input is applied, but these circuits will retain the output after the input is removed. Basically, they “remember” their last input condition.
- Combinational circuits
- Sequential circuits
The circuit below is nothing more than a single _____gate with its output tied to one input leg. The other input leg is tied to a switch. The switch is used to apply either ground or 5 volts. The line tying the output to the input is called a ______ line . The purpose of this line is to provide a path for the output of the gate to be returned to the input.
The circuit below is nothing more than a single OR gate with its output tied to one input leg. The other input leg is tied to a switch. The switch is used to apply either ground or 5 volts. The line tying the output to the input is called a feedback line. The purpose of the feedback line is to provide a path for the output of the gate to be returned to the input.
In a sequential circuit, the feedback line is the defining factor. It allows the gate to ________
In a sequential circuit, the feedback line is the defining factor. It allows the gate to “remember” its previous output.
Circuits composed of logic gates that have no feedback lines are called _______.
combinational circuits
Feedback lines are used to tie the _______.
output of a gate back to an input
A _____ changes states when its inputs are changed. A _____ can only change states when the clock pulse is changed.
A latch changes states when its inputs are changed. A flip-flop can only change states when the clock pulse is changed.
The basic _____ is constructed of two gates (either NOR or NAND gates or their equivalents) with the feedback lines cross-coupled between the gates.
The basic latch is constructed of two gates (either NOR or NAND gates or their equivalents) with the feedback lines cross-coupled between the gates.
An active-HIGH input RS latch is constructed of two _____ gates.
An active-HIGH input RS latch is constructed of two NOR gates.
An active-LOW input RS latch (RS latch) is constructed of two _____ gates.
An active-LOW input RS latch (RS latch) is constructed of two NAND gates.
Latches and flip-flops have two outputs, designated as Q and Q (spoken as either “_____” or “______”). Ideally, the output state of Q and Q should be opposite at all times. These opposite outputs are also known as complementary outputs.
Latches and flip-flops have two outputs, designated as Q and Q (spoken as either “Q NOT” or “NOT Q”). Ideally, the output state of Q and Q should be opposite at all times. These opposite outputs are also known as complementary outputs.
When a latch’s Q output is HIGH and its Q output is LOW, the latch is considered_____. This output state is also referred to as the HIGH or 1 state.
When a latch’s Q output is HIGH and its Q output is LOW, the latch is considered SET. This output state is also referred to as the HIGH or 1 state.
When a latch’s Q output is LOW and its Q output is HIGH, the latch is considered _____ This output state is also referred to as the LOW or 0 state.
When a latch’s Q output is LOW and its Q output is HIGH, the latch is considered RESET. This output state is also referred to as the LOW or 0 state.
These two output states coincide with the _____ and ______ inputs.
These two output states coincide with the “S” (SET) and “R” (RESET) inputs.
On the occasion that both outputs are the same, the terms most frequently used for the output condition are: “______________”.
On the occasion that both outputs are the same, the terms most frequently used for the output condition are: “ILLEGAL”, “UNDESIRED”, and “INVALID”.
Schematically, latches are indicated by either a _____ of the circuit (the two cross-coupled gates) or a ______ (rectangular box).
Schematically, latches are indicated by either a logic diagram of the circuit (the two cross-coupled gates) or a logic symbol (rectangular box).
The ______ is constructed of two cross-coupled NOR gates. The feedback lines extend from the output of each gate to one input leg of the opposite gate.
RS latch
The two inputs are SET (S) and RESET (R) and the two outputs are Q and Q. Remember that when the latch is SET, Q is ___and Q is ___. When the latch is RESET, Q is ___ and Q is ____.
The two inputs are SET (S) and RESET (R) and the two outputs are Q and Q. Remember that when the latch is SET, Q is 1 and Q is 0. When the latch is RESET, Q is 0 and Q is 1.
The RS latch is made from two cross-coupled _______.
nor gates
The _____ flip-flop is designed to store the last input condition until the next input condition is gated through. They have two inputs and two outputs.
D-type flip-flop
A HIGH applied to the___ or D input sets the output state to a ____ Q when the clock input is HIGH.
A HIGH applied to the DATA or D input sets the output state to a HIGH Q when the clock input is HIGH.
A ____ applied to the D input sets the output state to a LOW Q when the clock input is HIGH.
A LOW applied to the D input sets the output state to a LOW Q when the clock input is HIGH.
The RS flip-flop is designed to store the last input condition until ________.
What does RS stand for?
The RS (RESET-SET) flip-flop is designed to store the last input condition until the next input condition is applied.
The RS flip-flop has two inputs and two outputs. A _____ applied to the S (SET) input sets the output Q HIGH and output Q LOW.
The RS flip-flop has two inputs and two outputs. A HIGH applied to the S (SET) input sets the output Q HIGH and output Q LOW
A _____ applied to the R (RESET) input sets the output Q LOW and output Q HIGH.
A HIGH applied to the R (RESET) input sets the output Q LOW and output Q HIGH.
What happens if a HIGH is applied to inputs S and R at the same time?
If a HIGH is applied to inputs S and R at the same time, an illegal state exists. The outputs Q and Q cannot be determined.
An application for the RS flip-flop is as a replacement for the ________.
An application for the RS flip-flop is as a replacement for the mechanical switch.
Mechanical switches physically vibrate or bounce several times before a solid contact is made. Bouncing of the switch causes voltage spikes that can affect digital circuit operation. The RS flip-flop acts as an electrical switch. There is no mechanical bounce produced by the flip-flop.
The JK flip-flop is designed to store its last input conditions until _________.
The JK flip-flop is designed to store its last input conditions until the next input conditions are applied.
RS flip-flops have __ inputs and __ outputs.
JK flip-flops have __ inputs and __ outputs.
RS flip-flops have 2 inputs and 2 outputs.
JK flip-flops have 5 inputs and 2 outputs.
“CLK” is a label used to denote the ____. You may also see it labeled as CK, C, or CP.
Clock Input
Like a traffic light synchronizes the movement of vehicles at an intersection, the clock of a flip-flop is used to ________.
synchronize the transfer of data through the flip-flop.
As with the D-type flip-flop, the ___ and _____ inputs will override any other input conditions on the JK flip-flop. Regardless of the operation taking place, this will either SET or RESET the flip-flop.
PRESET and CLEAR
PRESET - A condition where a flip-flop’s outputs have Q HIGH and Q LOW. This condition may be considered as: PRESET = SET.
CLEAR - A condition where a flip-flop’s outputs have Q LOW and Q HIGH. This condition may be considered as: CLEAR = RESET.
The J and K inputs of the flip-flop are ____ dependent. That is, no data on these inputs will be processed by the flip-flop unless the____ input has been satisfied. These are called ______ inputs.
The J and K inputs of the flip-flop are clock dependent. That is, no data on these inputs will be processed by the flip-flop unless the clock input has been satisfied. These are called synchronous inputs.
SYNCHRONOUS - Having a fixed time relationship. The output of a device changes state only at a specified point on a triggering input, such as a clock signal.
If J=0 and K=1 when the negative edge of the clock pulse is applied, the Q output will go ____ and the Q output will go _____. The flip-flop will be in a _____ condition.
If J=0 and K=1 when the negative edge of the clock pulse is applied, the Q output will go LOW and the Q output will go HIGH. The flip-flop will be in a RESET condition.
If J=1 and K=0 when the negative edge of the clock pulse is applied, the Q output will go ___ and the Q will go _____. The flip-flop will be in the _____ condition.
if J=1 and K=0 when the negative edge of the clock pulse is applied, the Q output will go HIGH and the Q will go LOW. The flip-flop will be in the SET condition.
The final input possibility to be considered is when J and K are both HIGH. It is this condition that makes the JK flip-flop so important and unique. The truth table shows that under the J=1, K=1 condition, the Q and Q outputs will _________.
will reverse from whatever condition they were in prior to the clock pulse
For as long as the J and K inputs are held HIGH, every time the clock input is pulsed, the outputs will _____.
For as long as the J and K inputs are held HIGH, every time the clock input is pulsed, the outputs will reverse.
Fill in the missing outputs for the JK truth table.
Answer:
The “toggle” condition can be created in other flip-flops by _________.
The “toggle” condition can be created in other flip-flops by cross-connecting their outputs to their opposing input(s).
The symbol next to CLK indicates what?
The symbol on the clock (CLK) input indicates that the flip-flop is a positive edge triggered device.
