Bus Systems Flashcards
The basic bus system block diagram is comprised of what four parts?
Microprocessor (CPU/controller), System Memory, and System Input/Output.
A bus line is a conductor or conductive solder path that connects ______.
A bus line is a conductor or conductive solder path that connects multiple components, functions, or systems.
The ____ bus transmits and receives bytes of data and instructions. The word size (8-bit, 16-bit, 32-bit, etc.) determines the number of conductors required. An 8-bit data bus requires 8 parallel lines.
Data bus
The ____ bus is bi-directional and carries information to and from system components. Direction of data flow is determined by the control signals generated in the microprocessor.
Data bus
The CPU selects a path on the _____ bus using control signals. The information requested is transmitted to or from the CPU on the data bus.
Address Bus
The size of the address bus is determined by the ______ of the total system.
The size of the address bus is determined by the memory capacity of the total system. For example, a 64 K memory would require 16 separate address lines.
The ____ bus is unidirectional. It carries the synchronization and enable signals necessary to allow flow of information.
Control Bus
The ____ bus carries information describing what operation is to be performed, and which units are to respond. Signals include timing, memory read/write, and I/O read/write.
Control Bus
System components utilizing buses avoid massive interference by the application of ____, and _____. The CPU/controller contains the ____ for precise timing of the system.
System components utilizing buses avoid massive interference by the application of gates, and precise timing. The CPU/controller contains the clock for precise timing of the system.
Each component is connected to each bus wire through a gating network which consists of hundreds of _____ gates.
AND gates.
One input of each gate connects to a specific bus line, the second to a timing source, and the third to the control section. The information on the bus line is passed only when its AND gate is ______.
enabled.
System Memory
Memory is divided into three types; ____ (ROM), _____ (RAM), and ______ .
System Memory
Memory is divided into three types; read-only memory (ROM), random-access memory (RAM), and single word locations (registers).
_____contains the necessary steps required to sequence the CPU through initialization. This is permanent memory and does not change or erase when power is removed.
ROM contains the necessary steps required to sequence the CPU through initialization. ROM is permanent memory and does not change or erase when power is removed.
This memory may be manipulated under program control. The data in this memory is lost when power is removed.
(RAM) random access memory
RAM and ROM are housed in arrays of storage cells. These may be accessed by the CPU in groups of eight cells (8-bit bytes) called ______.
RAM and ROM are housed in arrays of storage cells. These may be accessed by the CPU in groups of eight cells (8-bit bytes) called addresses.
The ______ determines whether to decode (READ) or store (WRITE) the information at the accessed location.
The CPU/controller determines whether to decode (READ) or store (WRITE) the information at the accessed location.
What type of memory is inside the microprocessor and is provided for information manipulation? It also provides temporary storage of information.
Single word memory (registers)
The ______ contains all the functional sections found in a conventional general-purpose computer. It contains the control section that determines data flow in a bus system.
Microprocessor (CPU/Controller)
The _____ section interfaces external sources to the system bus. Keyboards, monitors, disk-drives, hard-drives, and printers interface with the control section via the I/O section.
input/output section
Address Bus
What memory is considered permanent and contains the initialization instructions?
ROM
Which of the following does the CPU contain?
RAM
Single Word Locations
ROM
Single Word Locations
ROM (Read Only Memory) is permanent memory and contains the instructions required to sequence the CPU.
RAM (Random Access Memory) is general purpose memory and is not contained with the CPU chip.
Which system bus is bi-directional to allowing intelligence transfer in each direction?
Control Bus
Data Bus
Address Bus
Data Bus
The control bus is unidirectional and determines what operation is to be performed.
The address bus is unidirectional and contains a binary code representing the location of the next data to be used or the location of where data will be stored.
Aircraft ___ work similarly to the computer version. Instead of it connecting all of the components (CPU, ALU, Memory) located within the same computer case, it connects ____ components located throughout the aircraft.
Aircraft data busses work similarly to the computer data bus. Instead of the data bus connecting all of the components (CPU, ALU, Memory) located within the same computer case, the aircraft data bus connects avionics components located throughout the aircraft.
Aircraft data bus systems use _____ wire to connect each component in the system. For safety, most systems incorporate _____ ensure redundancy in the system.
Aircraft data bus systems use 24 gauge, two-wire, shielded twiste pair wire to connect each component in the system. For safety, most systems incorporate two data bus lines; an A and a B Bus, to ensure redundancy in the system. If one data bus fails, the other data bus provides the same data to the components.
Information from receiving devices such as air data computers, navigation systems, and flight control systems is sent to the _____ as directed by the _____.
Information from receiving devices such as air data computers, navigation systems, and flight control systems is sent to the flight data computers as directed by the bus controller.
The speed and amount of data that can be handled on the bus is dependent on what?
The speed and amount of data that can be handled on the bus is dependent on the type of data bus system installed. There are several types of data bus protocols used in aircraft applications including ARINC 429 (32-bit), ARINC 629 (64-bit), and the 1553 military data bus.
_______ defines terminology used in conjunction with bus system protocol, and describes the operational characteristics of the basic bus system and tri-state devices.
Basic Bus System Protocol defines terminology used in conjunction with bus system protocol, and describes the operational characteristics of the basic bus system and tri-state devices.
The _____ bus originates in the control section. It supplies inputs to the ______ (ALU), the on-chip memory sections and to external units.
The unidirectional control bus originates in the control section. It supplies inputs to the Arithmetic Logic Unit (ALU), the on-chip memory sections and to external units.
The unidirectional address bus also originates in the _____ section. The address routing is to both on-chip memory and external units.
control section.
All the functional sections of a CPU are connected to the ____. This allows bi-directional data flow to the ALU, memory, and external units.
Data Bus
Unidirectional buses interface with the system bus via ____. These _____ isolate the CPU from the external sources.
Unidirectional buses interface with the system bus via bus transmitters. These transmitters isolate the CPU from the external sources.
The bi-directional bus contains ____ and _____ that isolate signals traveling to and from the CPU.
The bi-directional bus contains receivers and transmitters that isolate signals traveling to and from the CPU.
_____ isolate the system bus from the CPU and _____ isolate the CPU from the system bus.
Receivers isolate the system bus from the CPU and transmitters isolate the CPU from the system bus.
To function independently, many microprocessors contain the program instructions and three different types of on-chip memory. What are the three different types of on-chip memory.
RAM,ROM, and Single Memory Register.
During power up or initialization four events typically occur.
First, ____ sequences the CPU through initialization. Second, ____ memory is cleared. Third, new information requiring manipulation is stored in _____. Fourth, information for the next program instruction is loaded into the _______.
First, ROM sequences the CPU through initialization. Second, RAM memory is cleared. Third, new information requiring manipulation is stored in RAM. Fourth, information for the next program instruction is loaded into the single word registers.
_____allow bi-directional data flow on a single bus. This is reduces bus size and cost, two buses are used in this diagram.
Tri-state devices allow bi-directional data flow on a single bus. This is reduces bus size and cost, two buses are used in this diagram.
The six basic logic gates have a tri-state logic gate equivalent.
Name the gates.
six basic logic gates
The only difference between a conventional and a tri-state buffer is the addition of the _____. This second input can be active HIGH or LOW.
The only difference between a conventional and a tri-state buffer is the addition of the enable line. This second input can be active HIGH or LOW.
In an active ____ tri-state buffer, when the enable is HIGH, the level on the input is passed to the output. It operates like a conventional buffer.
In an active HIGH tri-state buffer, when the enable is HIGH, the level on the input is passed to the output. It operates like a conventional buffer.
When the enable is set to ____ the device is placed in the floating state. It acts like an open switch completely disconnecting the input of the device from the output.
When the enable is set to LOW, the device is placed in the floating state. It acts like an open switch completely disconnecting the input of the device from the output.
In an active LOW tri-state buffer, when the enable is _____, the level on the input of the circuit is passed to the output. It then operates as a standard buffer.
In an active LOW tri-state buffer, when the enable is LOW, the level on the input of the circuit is passed to the output. It then operates as a standard buffer.
When the enable is set to ____, the device is placed in the floating state. The device acts like an open switch completely disconnecting the input of the device from the output.
When the enable is set to HIGH, the device is placed in the floating state. The device acts like an open switch completely disconnecting the input of the device from the output.
