1.1.1 Structure Of The Processor Flashcards

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1
Q

ALU

A

The ALU performs arithmetic and logical operations on the data

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2
Q

Control unit

A

The control unit controls and coordinates the activities of the CPU, directing the flow of data between the CPU and other devices

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3
Q

Register

A

Tiny areas of extremely fast memory, located in the CPU, normally designed for a specific purpose

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4
Q

PC (Program Counter)

A

A register in the control unit that holds the address of the next instruction to be executed

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5
Q

ACC (Accumulator)

A

A general purpose register that is used to hold the results of operations carried out in the ALU

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6
Q

MAR (Memory address register)

A

A register in the CPU that stores the address of the memory location currently in use.

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7
Q

MDR (Memory data register)

A

A register in the CPU that is used to temporarily store the data read from or written to memory.

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8
Q

CIR (Current instruction register)

A

A register in the control unit that stores the current instruction being executed, divided into operand and opcode

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9
Q

Busses

A

A bus is a set of parallel wires connecting two or more components of a computer.
Typically consists of 8, 16, 32 or 64 lines

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10
Q

Data bus

A

A bi-directional bus, transports data and instructions to and from system components

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11
Q

Address bus

A

Used to transmit the memory addresses specifying where data is to be sent to or retrieved from

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12
Q

Control bus

A

Carries control and command signals to and from component of a computer

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13
Q

Fetch-Decode-Execute

A

The complete process of retrieving an instruction from store, decoding it and carrying it out

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14
Q

CPU (Central processing unit)

A

The main part of the computer consisting of the registers, ALU and control unit

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15
Q

Clock speed

A

The number of clock cycles completed per second. The higher the clock speed the faster the computer may work

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16
Q

Core

A

A core is a complete processing unit within the CPU

17
Q

Cache

A

A small, but extremely fast type of RAM, located in the CPU chip

18
Q

Pipelining

A

Concurrently completing the fetch-decode-execute cycle of 3 separate instructions

19
Q

Von Neumann Architecture

A

Traditional computer architecture that has a shared memory and data bus used for both data and instructions

20
Q

Harvard architecture

A

A computer architecture with physically separate memories for instructions and data

21
Q

Contemporary architecture

A

Processing that uses Von Neumann architecture for main memory and Harvard architecture for cache, divided into instruction and data cache