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1
Q
A
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2
Q

,

data

A

messages to be shared between sender and receiver

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3
Q

,

what does protocols establish ?

A

Protocols establish accurate and appropriate meaning to the messages that are understood by both senders and receivers

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4
Q

,

is the physical connection dependent of the physical connection ?

A

▪ Physical connection that is independent of the messaging ▪ message sharing “connection” between applications at the sender and the receiver ▪ physical connection with signaling that represents the messages being transported

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5
Q

,

examples of the Physical connection

A

▪ Examples ▪ POTS - plain old telephone service ▪ Web servers and Web browsers

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6
Q

,

HTTP Request and Response

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagek0ehrx-14A5C8F0F660BC90423.png

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7
Q

,

Model of a Communication Channel

A
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8
Q

,

what are the limitations of communication tool

A

▪ Limitation as a communication tool is the varying message length ▪ Long messages could tie up a communication channel indefinitely creating problems for other messages that share that channel

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9
Q

,

what are the packets ?

A

* A group of related packets make up a single message ▪ Consist of data encapsulated by the packet header which contains information about the packet

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10
Q

,

what are the packets used ?

A

▪ Used to solve problems of channel availability and maximum utilization ▪ Equivalent to an envelope that contains pages of data

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11
Q

,

what is the packet Header named ?

A

▪ Also known as the preamble

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12
Q

,

what does the packet header contain?

A

▪ Contains * Description of the packet * Destination address of receiver * Source address of sender * Information about the data being sent

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13
Q

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Advantages of Packets?

A
  1. ▪ Simplifies operations and increases communications efficiency 2. ▪ Reasonable unit for routing of data 3. ▪ Alternative to dedicating a channel for the entire length of the message 4. ▪ Packets from several sources can share a single channel 5. ▪ Each sender/receiver pair appears to have a channel to itself 6. ▪ Receiving computer can process an entire block of data instead of a character or byte at a time 7. ▪ Simplifies synchronization of the sending and receiving systems by providing clear start and stop point
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14
Q

,

what is the communication channel ?

A

▪ The path for the message between two communicating nodes ▪ May include intermediate nodes that forward packets to the next node ▪ Interfaces at each end of the connection may be differen

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15
Q

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what is ▪ Links?

A

▪ A segment of a communication channel

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16
Q

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what is the bandwidth ?

A

▪ Bit rate of overall channel

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17
Q

,

what is ▪ Medium parts ?

A

▪ Guided – communications limited to a specific path ▪ Unguided – communications not limited to a specific path

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18
Q

,

A Multi-Link Channel

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image7sz7qx-14A5C9702F52BAAF49D.png

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19
Q

,

what are the ▪ Data transmission directionality?

A

▪ Simplex – messages are carried only in one direction ▪ Half-duplex – messages are carried in both directions but only one direction at a time ▪ Full duplex – messages are simultaneously carried in both directions

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20
Q

,

what are the numbers of connections ?

A

▪ Number of connections ▪ Point-to-point ▪ Multipoint

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21
Q

,

types of signaling ?

A

▪ Digital vs. Analog

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22
Q

,

what are End node interfaces types ?

A

▪ Wired or wireless Ethernet ▪ Bluetooth, WiMax, DSL or cable link, modem, etc.

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23
Q

,

what are the types of Packet Routing ?

A
  1. Circuit switching 2. Virtual circuit 3. Packet switching (datagram switching )
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24
Q

,

what are the circuit switching ?

A

▪ Circuit switching ▪ Dedicated channel between source and destination for duration of connection

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25
Q

,

what are the ▪ Virtual circuit

A

Virtual circuit ▪ A channel path that is used to send packets between two end nodes ▪ Intermediate nodes may be shared with other channel paths

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26
Q

,

what are the packet switching ?

A

▪ Packet switching (datagram switching) ▪ Each packet is routed from node to node independently based on various criteria

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27
Q

,

End-to-end channel with many possible paths through intermediate nodes diagram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_183-14A5C9FE5A17ACA9A06.png

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28
Q

,

Virtual Circuits in a Network diagram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_184-14A5CA0907B479F38C0.png

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29
Q

,

Connecting End Points through Links and Networks diagram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_185-14A5CA10D68611A3141.png

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30
Q

,

what are routers ?

A

▪ Specialized devices used to interconnect network and pass packets from one network to another

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31
Q

,

what ARE the operations

A

When packet arrives at input port Processor decides where packet is to be directed A switch is set to direct the packet to the correct output port

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32
Q

,

what are getaways and what do they do ?

A

▪ Same as routers but connect dissimilar networks together ▪ Convert packet headers for the dissimilar network

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33
Q

,

what are the Communication Models

A

▪ TCP/IP ▪ OSI

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34
Q

,

what are the network addressing

A

▪ Network Topology

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35
Q

,

what are the types of networks ?

A
  1. Local Area Networks 2. Backbone Networks 3. Metropolitan Area Networks 4. Wide Area Networks 5. Internet Backbones and the Internet 6. Piconets
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36
Q

,

how is the communication model is implemented ?

A

▪ Implemented as a hierarchical protocol stack ▪ Each layer of the stack at the sender node contributes information that is used by the corresponding peer layer at the receiver node

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37
Q

,

why different protocols for ?

A

Different protocols for the different aspects of communication

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38
Q

,

17 advantages of Separating tasks and including well defined interfaces between the tasks?

A

* Adds flexibility * Simplifies design of protocols * Permits modification or substitution of protocols without affecting unrelated tasks * Permits a system to select only the protocols needed for a particular application

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39
Q

,

18 TCP/IP?

A

Transmission Control Protocol/Internet Protocol

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40
Q

,

what does the TCP and IP encapasses ?

A

The TCP/IP protocol suite encompasses an integrated suite of numerous protocols that work together and guide all aspects of communication.

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41
Q

,

Operation of TCP/IP Model daigram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagepc57qx-14A5C6629A45FFCFD66.png

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42
Q

,

Application Layer (Layer 5) what does do ?

A

▪ Layer where message is created ▪ Includes any application that provides software that can communicate with the network layer

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43
Q

,

from what sockets are Originated ?

A

Originated with BSD UNIX

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44
Q

,

what does sockets provide ?

A

* Provide the interface between the application layer and transport layer * Used by applications to i nitiate connections and to send messages through the network * A means for adding new protocols and keeping the network facilities current in their offerings

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45
Q

,

example for sockets ?

A

Example: SCSI over IP

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46
Q

,

what does transport layer does ?

A

▪ Provides services that support reliable end-to-end communications ▪ Generates the final address of the destination ▪ Responsible for all end-to-end communication facilities ▪ Packetization of the message, breaking up of the message into packets of reasonable size takes place at this level

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47
Q

,

where does the Packetization of the message, breaking up of the message into packets of reasonable size takes place?

A

Transport Layer (Layer 4)

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48
Q

,

where does the Generates the final address of the destination?

A

Transport Layer (Layer 4

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49
Q

,

▪ Three different protocols of the Transport Layer (Layer 4)?

A

▪ TCP ▪ UDP ▪ SCTP

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50
Q

,

advantages of the TCP? (Transmission Control Protocol)

A

▪ Reliable delivery service ▪ Sending and receiving TCP each create a socket ▪ Control packets are used to create a full duplex connection between the sockets ▪ A single TCP service can create multiple connections that operate simultaneously by creating additional sockets as needed ▪ Routing is the responsibility of the network layer (layer 3

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51
Q

,

talk about the ▪ UDP (User Datagram Protocol)?

A

▪ Unreliable, connectionless service ▪ No acknowledgment of receipt by receiving node ▪ Example: streaming video

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52
Q

,

example of the UDP ?

A

▪ Example: streaming video

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53
Q

,

what is the SCTP ?

A

Similar to TCP but with improved fault tolerance and ability to transport multiple messages through the same connection

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54
Q

,

what is the Logical Connection View of TCP daigram ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagete8erx-14A5C7417561761BC1D.png

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55
Q

,

what is the Network layer called ?

A

▪ The TCP/IP network layer is also called the internetworking layer or the IP layer

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56
Q

,

what is the responsible for the network layer ?

A

Responsible for the addressing and routing of packets to their proper and final destination

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57
Q

,

traits of the network layers ?

A

▪ Unreliable, connectionless, packet switching service * Does not guarantee delivery nor check for errors

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58
Q

,

what are routers and getaways refereed to ?

A

Routers and gateways are sometimes referred to as level 3 switches to indicate the level at which routing takes place

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59
Q

,

what does the network layer do during Communications within a local network?

A

* No routing is required because nodes are directly addressable ▪ Physical addresses for corresponding IP addresses are looked up in a table ▪ IP appends a header with the physical address and passes the datagram to the data link layer (layer 2)

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60
Q

,

what does the network layer do Communications sent outside of the local network?

A

▪ At each intermediate node, the network layer removes the current node address and determines the next node address ▪ The new address is added to the packet and passed to the data link layer (layer 2)

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61
Q

,

what does the Data Link Layer (Layer 2) do ?

A

▪ Responsible for the reliable transmission and delivery of packets between two adjacent nodes

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62
Q

,

what are packets called in the data link layer ?

A

n Packets at this layer are called frames

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63
Q

,

What are the 2 sub layers of the Data link layer?

A
  1. software Logical Link Control (LLC) - establish control of logical links btwn local devices on network 2. hardware Media Access Control (MAC) - device use to control access to network medium
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64
Q

,

traits of the Software logical link control sublayer?

A

* Error correction, flow control, retransmission, packet reconstruction and IP datagram/frame conversions * Numbers frames and reorders received frames to recreate the original message * Rarely used

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65
Q

,

what are the traits of the Hardware medium-access control sublayer?

A

* Defines procedures for access the channel and detecting errors * Responsible for services such as data encoding, collision handling, synchronization, and multiplexing

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66
Q

,

what takes place at the physical layer ?

A

Layer at which communication actually takes place consisting of a bare stream of bits

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67
Q

,

where is the physical layer implemented ?

A

▪ Primarily implemented in hardware by a network interface controller (NIC)

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68
Q

,

in the physical layer what does the Physical access protocol includes?

A

▪ Definition of the medium ▪ Signaling method, signal parameters, carrier frequencies, lengths of pulses, synchronization and timing issues ▪ Method used to physically connect the computer to the medium

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69
Q

,

Passing a Message Through an Intermediate Node diagram ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image1n3irx-14A5C86D25F4E8764EC.png

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70
Q

,

OSI Model what does it stand for ?

A

Open Systems Interconnection Reference Model was created by the International Standards Organization (ISO)

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71
Q

,

is it important the OSI model ?

A

▪ Although a conceptually important model, OSI is not widely accepted or used for actual communication

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72
Q

,

how many layers the OSI consists of ?

A

▪ Contains seven layers instead of five ▪ The application layer in the TCP/IP model is essentially represented by three layers in the OSI model ▪ Application layer ▪ Presentation layer ▪ Session layer

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73
Q

,

Comparison of OSI and TCP/IP diagram ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image5xcbrx-14A5C8971A233C5B7A8.png

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74
Q

,

what is OSI Presentation Layer Different protocols for the different aspects of communication

A

▪ Responsible for presenting data at the destination with the same meaning and appearance as it would have at the source ▪ Provides common data conversions and transformations that allow systems with different standards to communicate

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75
Q

,

what does OSI Presentation Layer include ?

A

Includes services such as data compression and restoration, encryption and decryption, data reformatting, ASCII-Unicode conversion, etc.

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76
Q

,

what does the OSI session layer establishes ?

A

▪ Establishes a dialogue between two cooperating applications or processes at the ends of the communication link

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77
Q

,

what is OSI Session Layer ▪ Responsible for?

A

▪ Establishing the session between the applications ▪ Controlling the dialogue ▪ Terminating the session

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78
Q

,

examples of the OSI session layer are ?

A

Examples ▪ Remote login ▪ Print spooling to remote printer

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79
Q

,

TCP/IP Addressing (1) what type of addresses used ?

A

▪ User friendly addresses ▪ URL – www.youtube.com ▪ Email – somebody@yahoo.com ▪ Printer name on the network

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80
Q

,

what is the domain name ?

A

▪ Standard global domain name system provides global scope for user friendly addresses ▪ Hierarchical system for name creation and registration ▪ Tools for locating and identifying specific names

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81
Q

,

traits of port addresses TCP/IP addressing ?

A

▪ Port Addresses (port numbers) ▪ Transport layer uses to identify the application that is to receive the message

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82
Q

,

what is the length of the port addressed ?

A

▪ 16 bits in length

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83
Q

,

example of the length of the port addresses ?

A

Example: port 80 is commonly used for Web services ▪ First 1024 numbers are called well-known ports because they are standard addresses specified for most common applications

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84
Q

,

what is the defined port numbers are also available to ??

A

applications

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85
Q

,

example of the ▪ Port Addresses (port numbers)

A

▪ For example, the following Web service uses the user- defined port of 8080 http://www.somewhere.org:8080/hiddenServer/index.html

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86
Q

,

daigram of the Well-Known Port Addresses

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagerdyfrx-14A5CB2B5880C66AB04.png

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87
Q

,

TCP/IP Addressing (3)▪ IP addresses ▪ IP addresses traits of IPv4 ?

A

* 32-bit addresses arranged as 4 octets, delimited by dots * Each octet is written as a decimal number between 0 and 255 * Example: 208.80.152.2 (Wikipedia’s IP address)

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88
Q

,

traits of IPv6

A

* Intended to eventually supplant IPv4 to provide additional IP addresses * 128-bit addresses arranged as 8 groups of four-digit hexadecimal * numbers separated by colons * Leading zeros and zero values in one or more consecutive groups may * be eliminated * Example: 6E:2A20::35C:66C0:0:5500 is the same as * 006E:2A20:0000:0000:035C:66C0:0000:550

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89
Q

,

TCP/IP Addressing (4) what is ▪ Domain name translation

A

▪ Translate a user friendly address into an IP address and port address for the transport layer ▪ Utilizes a global domain name directory servic

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90
Q

,

what does ▪ Address resolution protocol (network layer) do ?

A

▪ Translates IP addresses into physical addresses

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91
Q

,

what is ▪ MAC (medium-access control) address

A

▪ Most common type of physical address ▪ Every manufactured device that may connect to a network anywhere in the world is supplied with a permanent, unique MAC address ▪ Format consists of 48 bits arranged as 6 two-digit hexadecimal numbers separated by colons ▪ Example: 00:C0:9F:6C:F9:D0

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92
Q

,

diagram of the Different Addresses Used in a Network

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagev46erx-14A5CB78A12613DFA9F.png

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93
Q

,

what is Network Topology

A

Fundamental layout of a network

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94
Q

,

what does Network Topology describe ?

A

▪ Describes the path or paths between any two points in the network ▪ Affects availability, speed and traffic congestion of the networ

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95
Q

,

types of Network Topology?

A

▪ Logical topology – operational relationship between the various network components ▪ Physical topology – actual layout of the network wiring

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96
Q

,

Automobile Traffic Scenarios

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image07jyqx-14A5CB9640831CF86F6.png

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97
Q

,

Four Network Topologies

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagel4lirx-14A5CBA0E840A72887B.png

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98
Q

,

what is Mesh Topology

A

Multiple paths between end nodes

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99
Q

,

what are the limitations of the mesh topology ?

A

▪ Failure of an individual intermediate node will slow but not stop the network as long as an alternative path is available

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100
Q

,

▪ Large networks that use switches and routers are typically

A

partial mesh networks

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101
Q

,

Full mesh network

A
  1. Direct point-to-point channel connecting every pair of nodes 2. Impractical due to the large number of connections needed 3. Number of connections = nodes x (nodes – 1) / 2 4. 500 computer nodes would require 125,000 interconnecting cables
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102
Q

,

Five-Node Full Mesh Network diagram ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageaw4hrx-14A5CBE06FF76B1A028.png

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103
Q

,

how is the lay of the bus topology ?

A

▪ To communicate, each node “broadcasts” a message that travels along the bus ▪ Every node on the bus receives the message but it is ignored by all nodes except the one whose node matches the delivery address in the message

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104
Q

,

what does the transmission of the bus Topology ?

A

▪ Transmission from any stations travels entire medium (both directions) ▪ Termination required at ends of bus to prevent the signal from echoing

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105
Q

,

can Branches be added to a bus?

A

Branches can be added to a bus, expanding it into a tree but messages are still broadcast throughout the entire tree

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106
Q

,

how to implement bus network?

A

▪ Only requires a single pair of wires from one end of the network space to the other

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107
Q

,

advantage of the bus network ?

A

▪ Easiest to wire of the network topologies ▪ Low cost

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108
Q

,

issues of the bus network?

A

▪ Traffic congestion is a major issue

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109
Q

,

why bus network Rarely used in designs of new networks except for wireless networks?

A

▪ Because of the unguided nature of radio waves, wireless networks require some form of bus topology

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110
Q

,

when does the star network used?

A

▪ Primarily used for local area networks and sometimes used to connect satellite offices to a central office

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111
Q

,

how is the nodes connected in the star topology?

A

▪ All nodes are connected point-to-point to a central device ▪ Nodes communicate through the central device ▪ Switching in the central device connects pairs of nodes together to allow them to communicate directly

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112
Q

,

what does the Central device of the star topology?

A

Central device can steer data from one node to another as required

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113
Q

,

is it possible to switch multiple pairs

A

▪ Most modern switches allow multiple pairs to communicate simultaneously

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114
Q

,

limitations of the star topology ?

A

▪ Failure of central device causes entire network to go down

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115
Q

,

how Ring Topology works

A

▪ Point-to-point connection from each node to the next ▪ Last node is connected back to the first to form a closed ring ▪ Each node retransmits the signal that it receives from the previous node in the ring ▪ Packets are placed on the loop at a node, and travel from node to node until the desired node is reached

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116
Q

,

Although the ring is inherently unidirectional, it is possible to build a

A

bidirectional ring network

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117
Q

,

is it popular in the past Ring topology?

A

▪ Popular in the past because they provided a controlled way in which to guarantee network performance ▪ Legacy token-ring local area networks ▪ Used in some FDDI fiber optic backbone and metropolitan area networks

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118
Q

,

what is Local Area Networks (LAN)?

A

▪ A network that connections computers and other supporting devices over a relatively small localized area

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119
Q

,

what is the size of Local Area Networks (LAN)?

A

▪ Typically ranging in size from a single room to multiple buildings in close range of each other ▪ Most of the computers are personal computers or workstations

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120
Q

,

is Routers and perhaps gateways are used to connect the LAN

A

▪ Routers and perhaps gateways are used to connect the LAN to other networks

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121
Q

,

how to minimize extraneous traffic on the network?

A

Creating separate LANs for different departments or for different business functions is done to minimize extraneous traffic on the network

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122
Q

,

what protocol LAN is base on?

A

Most modern LANs are based on one of the Ethernet protocol standards

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123
Q

,

Common Ethernet Standards diagram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageoylhrx-14A5D0DDE8D65A8F480.png

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124
Q

,

what is the Ethernet Hubs based on ?

A

Based on bus topology

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125
Q

,

how to to simplify wiring and maintenance in Ethernet Hubs?

A

▪ A passive central connection device used to simplify wiring and maintenance

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126
Q

,

what does the physical layer does in the Ethernet Hubs ?

A

▪ Physical layer device where all of the connections are tied together inside the hub

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127
Q

,

how the signaling of the Ethernet Hubs ?

A

▪ Signals are broadcast to every device connected to the hub

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128
Q

,

what are MACP in the Ethernet Hubs ?

A

Uses the CSMA/CD medium access control protocol

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129
Q

,

why is the hubs in the Ethernet is declining

A

Use of hubs is declining because switches often provide better performance

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130
Q

,

Ethernet Switches what topology it uses ?

A

Logically a star topology, not a bus topology

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131
Q

,

the ability of the Ethernet switches ?

A

▪ Able to set up a direction connection between any two nodes ▪ Multiple pairs of nodes can communicate at the full bandwidth

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132
Q

,

what method is Ethernet Switches ?

A

Prevalent method for wired local area networks

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133
Q

,

Hub vs. Switch Based Ethernet

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_190-14A5D173432698D08C7.png

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134
Q

,

Wireless Ethernet (WiFi) how

A

* Radio-based compatible extension to the Ethernet standard ▪ Central access point is similar to a hub but is an active node ▪ Central access point transmits and receives radio waves to communicate with the nodes

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135
Q

,

Radio space requirement ?

A

▪ Radio space must be shared between the nodes

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136
Q

,

why is the Wireless Ethernet (WiFi) Does not use the CSMA-CD protocol?

A

Does not use the CSMA-CD protocol because it is possible for units to be far away that although they can communicate with the access point, they cannot detect one another

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137
Q

,

Wireless Ethernet Characteristics

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagew7ebrx-14A5D1D7EFD0AF1736A.png

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138
Q

,

Wireless Mesh Network

A

Mesh points operate at the medium-access control layer and do not require wiring

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139
Q

,

what is Backbone Networks also called ?

A

Also called tiered Ethernet

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140
Q

,

what does the backbone networks do ?

A

▪ Ties together LANs and provides access to external networks like the Internet

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141
Q

,

what is the Chief motivation of Backbone Networks ?

A

Chief motivation is to improve overall performance of a larger network by creating separate networks for groups of users who primarily communicate with one another

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142
Q

,

when in the backbone networks Communicate between the LANs is enabled?

A

Communicate between the LANs is enabled only when necessary

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143
Q

,

did you know that

A

in Backbone Networks Overall range of the network can be extended beyond the limits of a single LAN Can be viewed as a large LAN where each node is itself a LAN

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144
Q

,

example of the backbone networks ?

A

Intranets – an organizational network where user interfaces and applications are primarily based on Web services

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145
Q

,

Backbone Network

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageeekerx-14A5D2543935633B090.png

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146
Q

,

what is the Metropolitan Area Networks?

A

A network larger in geographical scope than a LAN but within a range of less than 30 miles or 50 km

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147
Q

,

did you know that there is Often there is a desire to create network links to link locations

A

that would require running wires through someone else’s property.

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148
Q

,

how does MAN works

A

▪ Requires services from a service provider or public carrier ▪ Begins to resemble a WAN ▪ Edge connection – a connection at an access point on the customer’s premises that connects to a provider

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149
Q

,

what is Campus area network (CAN) ?

A

▪ Network type between a LAN and a MAN ▪ Number of interconnected buildings clustered together

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150
Q

,

Metropolitan Area Network

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageju36qx-14A5D28CBCB4208E85A.png

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151
Q

,

what is Wide Area Networks (WAN) ?

A

▪ Facilitate communications between users and applications over large geographical distances ▪ Distinguishing feature is the extensive reliance on service providers to provide the required connectivity between nodes

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152
Q

,

how is the carrier network represented by in WAN?

A

The carrier network is sometimes represented as a collection of private virtual networks

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153
Q

,

Primary reasons for WANs

A

▪ Organization requires data communication links between widely spread facilities and between an organization and its external contacts ▪ Organization requires fast access to the Internet, either as a consumer or as a provider of Internet services, or both

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154
Q

,

what is an example in WAN?

A

Extranet ▪ A connection between a business and its business partners that usually uses the Internet as a medium for its activities

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155
Q

,

Two Real-World WANs

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image1zuzqx-14A5D2CFDF421B98E74.png

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156
Q

,

Wide Area Network Carrier Options

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image38aerx-14A5D2D8B8D48804881.png

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157
Q

,

what does (ISPs) do ?

A

Internet Service Providers

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158
Q

,

traits of the Internet backbone?

A

▪ High speed fiber optic networks that carry traffic between major cities throughout the world ▪ Speed ranges from 45 to 625 Gbps with faster backbones in the future ▪ Created to speed network traffic that would otherwise require many slow hops to the final destination ▪ No official central backbone and no official guidance for its development

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159
Q

,

what does the Network access points do in the backbone ?

A

Interchanges between the backbones

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160
Q

,

DID you know

A

▪ Local ISPs receive their service from regional ISPs who, in turn, receive their service from national ISPs Most regional ISPs also interconnect among themselves

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161
Q

,

Comparison of Internet and Highway Architecture

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagep16frx-14A5D312EAE3EA6EDA5.png

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162
Q

,

what is Piconets also known as >?

A

Also known as personal area networks (PAN) Created for the personal use of an individual

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163
Q

,

what is the pictonets range of?

A

▪ Generally have ranges of 30 feet or less which is sufficient to permit an individual to interconnect personal computing devices ▪ Connections between different cooperating users are possible but rare

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164
Q

,

what is the primary medium for PANs?

A

Bluetooth

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165
Q

,

example of the PANS ?

A

▪ Example: interconnection between a cell phone, hands-free speaker and car radio

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166
Q

,

ISO

A

(International Standards Organization) ▪ > 17,000 standards including the OSI Reference model

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167
Q

,

IEEE

A

* (Institute for Electrical and Electronics Engineers ▪ Ethernet standards – Ethernet (802.3), Wi-Fi (802.11), Bluetooth (802.15) and WiMax (802.16)

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168
Q

,

what does ▪ IETF stands for ?

A

IETF (Internet Engineering Task Force) ▪ Internet standards based on RFCs (request for comments)

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169
Q

,

what does ICANN stand for ?

A

ICANN ▪ Internet Corporation for Assigned Names and Numbers ▪ IP address allocation, domain name registration, protocol parameter assignment ▪ Management of domain name and root server systems

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170
Q

,

what does IANA stands for ?

A

(Internet Assigned Numbers Authority ▪ Registers application layer port numbers and specific parameter values used in Internet protocol headers

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171
Q

,

Numbers can be represented as a combination of

A

▪ Value or magnitude ▪ Sign (plus or minus) ▪ Decimal (if necessary)

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172
Q

,

Value Range: Binary vs. BCD

A

▪ BCD range of values < conventional binary representation

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173
Q

,

Value Range: Binary vs. BCD how ?

A

▪ Binary: 4 bits can hold 16 different values (0 to 15) ▪ BCD: 4 bits can hold only 10 different values (0 to 9)

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174
Q

,

Conventional Binary why prefered ?

A

▪ Binary representation generally preferred ▪ Greater range of value for given number of bits ▪ Calculations easier

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175
Q

,

where BCD is used ?

A

BCD often used in business applications to maintain decimal rounding and decimal precision

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176
Q

,

Simple BCD Multiplication

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageh9m7qx-14A62F9928F3EC59B43.png

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177
Q

,

how is packed decimal format ?

A

▪ Real numbers representing dollars and cents ▪ Support by business-oriented languages like COBOL ▪ IBM System 370/390 and Compaq Alpha

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178
Q

,

Signed-Integer Representation how ?

A

▪ No obvious direct way to represent the sign in binary notation

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179
Q

,

what options are Signed-Integer Representation ?

A

Options: ▪ Sign-and-magnitude representation ▪ 1’s complement ▪ 2’s complement (most common)

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180
Q

,

Sign-and-Magnitude how ?

A

▪ Use left-most bit for sign ▪ 0 = plus; 1 = minus ▪ Total range of integers the same ▪ Half of integers positive; half negative ▪ Magnitude of largest integer half as large

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181
Q

,

example of the sign and magnitude

A

▪ Example using 8 bits: ▪ Unsigned: 1111 1111 = +255 ▪ Signed: 0111 1111 = +127 1111 1111 = -127 Note: 2 values for 0: +0 (0000 0000) and -0 (1000 0000)

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182
Q

,

Difficult Calculation Algorithms

A

▪ Sign-and-magnitude algorithms complex and difficult to implement in hardware ▪ Must test for 2 values of 0 ▪ Useful with BCD ▪ Order of signed number and carry/borrow makes a difference ▪ Example: Decimal addition algorithm

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183
Q

,

Instruction Set Architectures, what do it do?

A

ISA ISA determines instruction formats

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184
Q

,

– The LMC is a

A

one-address architecture (an accumulator-based machine).– e.g., the instruction ADD X

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185
Q

,

other instructions set and why

A

There are other instruction set architectures, all based on the number of explicit operands . 0-address (stack) 1-address (accumulator) 2-address 3-addres

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186
Q

,

0-Address Machines

A

– All operands for binary operations are implicit on the stack. Only push/pop reference memory. – e.g., calculating a = a * b + c – d * e

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187
Q

,

1-Address Machines

A

Accumulator is a source and destination. Second source is explicit.

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188
Q

,

1-Address Machines

A

10 memory references, not including instruction fetch

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189
Q

,

2-Address Machines

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_245-14A61F370A37A2BD282.png

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190
Q

,

2-Address Machines

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_246-14A61F45B74229CEDAE.png

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191
Q

,

2-Address Machines with registers ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_247-14A61F50C171EEB8E26.png

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192
Q

,

3-Address Machines

A

– One destination operand, two source operands, all explicit

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193
Q

,

3-Address Machines eg without registers ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_248-14A61F622D5078C6512.png

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194
Q

,

3-Address Machines without registers?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_249-14A61F7191F1FB1AE34.png

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195
Q

,

6 memory accesses; general purpose registers make a substantial difference.

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_250-14A61F8185A11F9B07D.png

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196
Q

,

Comparison – Assume 8 registers (3 bits), * 32 op-codes (5 bits), 15-bit addresses, * 16-bit integers. – Which ISA accesses memory the least?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_251-14A61F9BCDF25EF0299.png

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197
Q

,

0-address

A

(stack)

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198
Q

,

1-address

A

(accumulator)

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199
Q

,

2-address

A

(register variant is 11⁄2-address)

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200
Q

,

3-address

A

(with register variant

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201
Q

,

The instruction set architecture determines

A

the format of instructions (and therefore the assembly language).

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202
Q

,

Four basic types with variations:?

A
  1. 0-address (stack) 2. 1-address (accumulator) 3. 2-address (register variant is 11⁄2-address) 4. 3-address (with register variant
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203
Q

,

ISA dramatically affects what ?

A

the number of times memory is accessed.

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204
Q

,

CISC

A

Complex Instruction Set Computers

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205
Q

,

RISC

A

Reduced Instruction Set Computers

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206
Q

,

Motivation for CISC

A

Early computers had very little and very slow memory. Thus, the fewer instructions fetched, the faster the computer could be.

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207
Q

,

General characteristics: CISC

A

High number of operations (300+) Compilers have less work to do to translate HLL into machine code. Large number of instruction formats Multi-clock cycle instructions Fewer registers; more memory access Large number of transistors, CPU complexity, therefore higher CPU prices

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208
Q

,

Motivation for RISC

A

As memory capacities grew, there was less need for high code density. Also, pushing clock rates higher on CISC hardware was difficult. A simpler processor could be clocked faster

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209
Q

,

– General characteristics of RISC

A
  1. Lower number of operations (150+) 2. Compilers have more work to do. 3. Small number of instruction formats 4. All instructions take one cycle. 5. Load/store architecture 6. Smaller number of transistors, lower CPU complexity, therefore lower CPU prices
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210
Q

,

RISC vs. CISC

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_252-14A6227F56E5A3FFFE5.png

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211
Q

,

did you know about transistor

A

– CISC processors require more CPU transistors in an effort to maximize code density in memory

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212
Q

,

did you know about the Risc processor

A

RISC processors use a simpler design in an effort to reduce the number of cycles per instruction

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213
Q

,

The only major CISC architecture today is

A

the Intel x86 and x64. Nearly all else is RISC.

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214
Q

,

CPU: Major Components

A

▪ ALU CU

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215
Q

,

ALU

A

arithmetic logic unit) ▪ Performs calculations and comparisons

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216
Q

,

CU

A

(control unit) ▪ Performs fetch/execute cycle Accesses program instructions and issues commands to the ALU Moves data to and from CPU registers and other hardware components

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217
Q

,

Subcomponents: of the CPU

A

Memory management unit: supervises fetching instructions and data from memory I/O Interface: sometimes combined with memory management unit as Bus Interface Unit

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218
Q

,

System Block Diagram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imaget5ujrx-14A623EF3484D1AD610.png

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219
Q

,

Concept of Registers

A

▪ Small, permanent storage locations within the CPU used for a particular purpose ▪ Manipulated directly by the Control Unit ▪ Wired for specific function ▪ Size in bits or bytes (not in MB like memory ▪ Can hold data, an address or an instruction

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220
Q

,

▪ How many registers does the LMC have? ▪ What are the registers in the LMC?

A

two the baskets

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221
Q

,

Use of Registers

A

▪ Scratchpad for currently executing program • Holds data needed quickly or frequently ▪ Stores information about status of CPU and currently executing program * Address of next program instruction * Signals from external devices

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222
Q

,

what about General Purpose Registers

A

User-visible registers Hold intermediate results or data values, e.g., loop counters Equivalent to LMC’s calculator Typically several dozen in current CPUs

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223
Q

,

Special-Purpose Registers (PC )

A

Program Count Register (PC) ▪ Also called instruction pointer

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224
Q

,

Special-Purpose Registers (IR)

A

Instruction Register (IR) ▪ Stores instruction fetched from memory

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225
Q

,

Special-Purpose Registers

A

▪ Memory Address Register (MAR) ▪ Memory Data Register (MDR)

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226
Q

,

Status Registers

A

▪ Status of CPU and currently executing program

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227
Q

,

▪ Flags

A

(one bit Boolean variable) to track condition like arithmetic carry and overflow, power failure, internal computer error

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228
Q

,

Register Operations

A

Stores values from other locations (registers and memory) ▪ Addition and subtraction ▪ Shift or rotate data ▪ Test contents for conditions such as zero or positive

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229
Q

,

Operation of Memory

A

▪ Each memory location has a unique address ▪ Address from an instruction is copied to the MAR which finds the location in memory ▪ CPU determines if it is a store or retrieval ▪ Transfer takes place between the MDR and memory ▪ MDR is a two way register

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230
Q

,

Relationship between MAR, MDR and Memory

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageyl64qx-14A6244FA592BD3F909.png

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231
Q

,

MAR-MDR Example

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagets74qx-14A6245FB8B15F5F3DA.png

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232
Q

,

Visual Analogy of Memory

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagewq1jrx-14A62465FD82D7612E8.png

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233
Q

,

Individual Memory Cell

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image5lihrx-14A6246EE3776B84806.png

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234
Q

,

memory capacity determined by two factors ?

A
  1. Number of bits in the MAR LMC = 100 (00 to 99) 2 K where K = width of the register in bits 2. Size of the address portion of the instruction 4 bits allows 16 locations 8 bits allows 256 locations 32 bits allows 4,294,967,296 or 4 GB
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235
Q

,

RAM:

A

Random Access Memory

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236
Q

,

what is RAM (Dynamic RAM)?

A

▪ Most common, cheap, less electrical power, less heat, smaller space ▪ Volatile: must be refreshed (recharged with power) * 1000’s of times each second

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237
Q

,

SRAM (static RAM)

A

▪ Faster and more expensive than DRAM ▪ Volatile ▪ Small amounts are often used in cache memory for high-speed memory access

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238
Q

,

Nonvolatile Memory?1

A

ROM ▪ Read-only Memory ▪ Holds software that is not expected to change over the life of the system

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239
Q

,

Nonvolatile Memory?2

A

▪ EEPROM ▪ Electrically Erasable Programmable ROM

240
Q

,

Nonvolatile Memory ?

A

Flash Memory * Faster than disks but more expensive * Uses hot carrier injection to store bits of data * Slow rewrite time compared to RAM * Useful for nonvolatile portable computer storage

241
Q

,

why two cycle process ?

A

▪ Two-cycle process because both instructions and data are in memory ▪ Fetch ▪ Decode or find instruction, load from memory into register and signal ALU ▪ Execute ▪ Performs operation that instruction requires ▪ Move/transform data

242
Q

,

LMC vs. CPU Fetch and Execute Cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagesk5zqx-14A624C2B34604CD684.png

243
Q

,

Load Fetch/Execute Cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_253-14A624D51252008153D.png

244
Q

,

Store Fetch/Execute Cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_254-14A624DD0947E3E69CB.png

245
Q

,

ADD Fetch/Execute Cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_255-14A624E59B9327AE000.png

246
Q

,

LMC Fetch/Execute

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_256-14A624ED42D413B7F75.png

247
Q

,

what is a bus?

A

▪ The physical connection that makes it possible to transfer data from one location in the computer system to another ▪ Group of electrical or optical conductors for carrying signals from one location to another ▪ Wires or conductors printed on a circuit board ▪ Line: each conductor in the bus

248
Q

,

▪ 4 kinds of signals buses ?

A
  1. Data 2. Addressing 3. Control signals 4. Power (sometime
249
Q

,

Bus Characteristics

A

Number of separate conductors Data width in bits carried simultaneously Addressing capacity Lines on the bus are for a single type of signal or shared Throughput - data transfer rate in bits per second Distance between two endpoints

250
Q

,

Bus Characteristics

A

Number and type of attachments supported Type of control required Defined purpose Features and capabilities

251
Q

,

Bus Categorizations

A

▪ Parallel vs. serial buses ▪ Direction of transmission ▪ Simplex – unidirectional ▪ Half duplex – bidirectional, one direction at a time ▪ Full duplex – bidirectional simultaneously ▪ Method of interconnection

252
Q

,

▪ Method of interconnection

A

▪ Point-to-point – single source to single destination • Cables – point-to-point buses that connect to an external device ▪ Multipoint bus – also broadcast bus or multidrop bus • Connect multiple points to one another

253
Q

,

Parallel vs. Serial Buses

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_257-14A6252FD871C12C7EA.png

254
Q

,

Point-to-point vs. Multipoint?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_258-14A6253D3BE69D10F44.png

255
Q

,

Classification of Instructions

A

▪ Data Movement (load, store) ▪ Most common, greatest flexibility ▪ Involve memory and registers ▪ What’s this size of a word ? 16? 32? 64 bits? ▪ Arithmetic ▪ Operators + - / * ^ ▪ Integers and floating point

256
Q

,

Classification of Instructions2

A

▪ Boolean Logic ▪ Often includes at least AND, XOR, and NOT ▪ Single operand manipulation instructions ▪ Negating, decrementing, incrementing, set to 0

257
Q

,

More Instruction Classifications

A

Bit manipulation instructions ▪ Flags to test for conditions Shift and rotate Program control Stack instructions Multiple data instructions I/O and machine control

258
Q

,

Register Shifts and Rotates

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageq7mcrx-14A6255ACE7362A80AA.png

259
Q

,

Program Control Instructions

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_259-14A6256C6882B957372.png

260
Q

,

Stack Instructions

A

▪ Stack instructions ▪ LIFO method for organizing information ▪ Items removed in the reverse order from that in which they are added

261
Q

,

Fixed Location Subroutine Return Address Storage: Oops!

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagejao1qx-14A6257C19A43059998.png

262
Q

,

Stack Subroutine Return Address Storage

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagejcs1qx-14A62582D275BF9888A.png

263
Q

,

Stack Subroutine Return Address Storage

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagejcs1qx-14A625918221CE1FD03.png

264
Q

,

Block of Memory as a Stack

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageko3brx-14A6259D73E4211963E.png

265
Q

,

Multiple Data Instructions

A

▪ Perform a single operation on multiple pieces of data simultaneously ▪ SIMD: Single Instruction, Multiple Data ▪ Commonly used in multimedia, vector and array processing applications

266
Q

,

Instruction Elements

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_260-14A625B3A3D2AB36CA7.png

267
Q

,

Instruction Format

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_261-14A625B1AE748A4B5BD.png

268
Q

,

▪ Instruction is ?

A

▪ Direction given to a computer ▪ Causes electrical or optical signals to be sent through specific circuits for processing

269
Q

,

Instruction set ?

A

▪ Design defines functions performed by the processor ▪ Differentiates computer architecture by the Number of instructions Complexity of operations performed by individual instructions Data types supported Format (layout, fixed vs. variable length) Use of registers Addressing (size, mode

270
Q

,

Instruction Word Size

A

▪ Fixed vs. variable size ▪ Pipelining has mostly eliminated variable instruction size architectures ▪ Most current architectures use 32-bit or 64-bit words ▪ Addressing Modes ▪ Direct Mode used by the LMC ▪ Register Deferred ▪ Also immediate, indirect, indexed

271
Q

,

Instruction Format Examples

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image0ah4qx-14A625E16832BEC9267.png

272
Q

,

What is a bus?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_262-14A626011877D139C3A.png

273
Q

,

what is bus

A

A line is a single conductor carrying an electrical signal between components. It carries one bit of information. – A bus is a collection of lines used to transfer multiple bits of information at a time. – The width of a bus is the number of lines

274
Q

,

compare Point-to-point vs. multipoint ?

A

– Point-to-point busses connect two components – Multipoint busses connect more than two component

275
Q

,

what is contention

A

Simplex busses transmit only in one direction. Half-duplex busses transmit in both directions but not simultaneously. Full-duplex busses transmit in both directions at the same time. If busses are not full duplex, then a protocol must control access to prevent collisions on the bus – CSMA/CD on Thinnet Ethernet (IEEE 802.3) – CSMA/CA on WiFi (IEEE 802.11)

276
Q

,

Busses carry what do they do ?

A

data from one component to another.

277
Q

,

The width of the bus determines

A

the number of bits at a time that can be transmitted.

278
Q

,

When the bus is half duplex or is multipoint, then an

A

an algorithm is needed to control access to the bus to prevent collisions.

279
Q

,

Generations of programming languages First generation

A

programmed directly in binary using wires or switches

280
Q

,

Generations of programming languages Second generation:

A

assembly language. Human readable, converted directly to machine code

281
Q

,

Third generation:?

A

: high-level languages, while loops, if-then-else, structured. Most programming today, including object-oriented

282
Q

,

Fourth generation:

A

1990s natural languages, non-procedural, report generation. Use programs to generate other programs. Limited use today.

283
Q

,

Key idea:

A

Regardless of the language of writing, computers only process machine code

284
Q

,

All non-machine code goes through a translation phase into machine code.

A

– Code generators – Compilers – Assemblers

285
Q

,

Language translation process

A

– High level languages use comparison constructs, loops, variables, etc. – Machine code is binary, directly executed by CPU

286
Q

,

– Convert high level language to if/goto.

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image5am5qx-14A6291A5844FDC48ED.png

287
Q

,

Language translation process – Convert high level language to if/goto

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_264-14A62922EE1562CD2AA.png

288
Q

,

Language translation process – Convert if/goto to assembly (LMC here).

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_265-14A6292DDD74C832AB4.png

289
Q

,

Convert if/goto to assembly (LMC here)

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_266-14A6293600A1D36199D.png

290
Q

,

you need to check and practice the code in chapter 6 and her virtual 6

A

yay xx

291
Q

,

did you know 1

A

– High level languages are convenient to read and write for human

292
Q

,

did you know 2

A

Computers execute only binary machine code.

293
Q

,

fun info

A

– Compilers translate high level languages to machine code. – Assemblers translate assembly language into machine code

294
Q

,

Use if/goto pseudo-code as

A

an intermediate language between high level and assembler

295
Q

,

The Little Man Computer

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageqm21qx-14A629DE19D42908DAE.png

296
Q

,

Mailboxes: Address vs. Content

A

▪ Addresses are consecutive starting at 00 and ending at 99

297
Q

,

contents of the mailbox

A

Content may be ▪ Data, a three digit number, or ▪ Instructions

298
Q

,

Content: Instructions Op code

A

▪ In LMC, represented by a single digit ▪ Operation code ▪ Arbitrary mnemonic

299
Q

,

Operand

A

▪ In LMC, represented by two digits following the op code ▪ Object to be manipulated Data or Address of data

300
Q

,

Content: Instructions

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_267-14A62A05ED42177BDC6.png

301
Q

,

what is the magic in the LMC?

A

▪ Load program into memory ▪ Put data into In Basket

302
Q

,

Assembly Language

A

▪ Specific to a CPU ▪ 1 to 1 correspondence between assembly language instruction and binary (machine) language instruction

303
Q

,

Mnemonics

A

(short character sequence) represent instructions

304
Q

,

when is assembly language used ?

A

▪ Used when programmer needs precise control over hardware, e.g.,device drivers

305
Q

,

Instruction Set

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_268-14A62A288205A258BFD.png

306
Q

,

Input/Output in LMC

A

Move data between calculator and in/out baskets

307
Q

,

did you know the LMC Input/Output

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_270-14A62A3E9147A50B6F3.png

308
Q

,

Internal Data Movement

A

▪ Between mailbox and calculator

309
Q

,

LMC Internal Data

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageagvkrx-14A62A506A96C951748.png

310
Q

,

Arithmetic Instructions

A

▪ Read mailbox ▪ Perform operation in the calculator

311
Q

,

LMC Arithmetic Instructions

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_273-14A62A657622C8B6376.png

312
Q

,

Data storage location

A

▪ Physically identical to instruction mailbox ▪ Not located in instruction sequence ▪ Identified by DAT mnemonic

313
Q

,

Simple Program: Add 2 Numbers

A

▪ Assume data is stored in mailboxes with addresses >90 ▪ Write instructions

314
Q

,

Program to Add 2 Numbers

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_275-14A62A8B62B5C5EF120.png

315
Q

,

Program to Add 2 Numbers: Using Mnemonics

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_276-14A62A96BAE5B15CCE4.png

316
Q

,

Program Control

A

▪ Branching (executing an instruction out of sequence) Changes the address in the counter

317
Q

,

LMC Instruction Set

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_278-14A62AB733F2F06F758.png

318
Q

,

Find Positive Difference of 2 Numbers

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_279-14A62AC00C109BFC399.png

319
Q

,

Instruction Cycle

A

▪ Fetch: Little Man finds out what instruction he is to execute ▪ Execute: Little Man performs the work.

320
Q

,

Fetch Portion of Fetch and Execute Cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_280-14A62AD1ED52BF1F673.png

321
Q

,

Fetch, cont.

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_281-14A62ADB10661F3D94C.png

322
Q

,

Execute Portion

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_282-14A62AE2DA379F437E6.png

323
Q

,

Execute, cont

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_283-14A62AEC8147E934B37.png

324
Q

,

von Neumann Architecture (1945)

A

▪ Stored program concept ▪ Memory is addressed linearly ▪ Memory is addressed without regard to content

325
Q

,

check the slides chapter week 5 instructions cycle

A

yay

326
Q

,

what are Peripherals?

A

Devices that are separate from the basic computer ▪ Not the CPU, memory, or power supply ▪ Classified as input, output, and storage

327
Q

,

how Peripherals connected ?

A

▪ Connect via ▪ Ports ▪ Interface to systems bus

328
Q

,

types of storage Devices ?

A

▪ Primary memory ▪ Secondary storage

329
Q

,

what are the Secondary storage include?

A

▪ Data and programs must be copied to primary memory for CPU access ▪ Permanence of data - nonvolatile ▪ Direct access storage devices (DASDs) ▪ Online storage ▪ Offline storage – loaded when needed ▪ Network file storage • File servers, web servers, database servers

330
Q

,

how is the speed measured in storage devices ?

A

Measured by access time and data transfer rate

331
Q

,

Access time:

A

average time it takes a computer to locate data and read it ▪ millisecond = one-thousandth of a second

332
Q

,

Data transfer rate:

A

amount of data that moves per second

333
Q

,

Storage Hierarchy Diagram ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageutgarx-14A5F4138920F20D2A1.png

334
Q

,

what are the Secondary Storage Devices

A
  1. Solid state memory 2. Magnetic disks 3. Optical disk storage 4. Magnetic tape 5. Network storage
335
Q

,

Characteristics of Secondary Storage Devices?

A

▪ Rotation vs. Linear ▪ Direct access vs. Sequential access

336
Q

,

what is falsh memory ?

A

▪ Nonvolatile electronic integrated circuit memory ▪ Similar to other read-only memory but uses a different technology

337
Q

,

what does Flash memory permit ?

A

▪ Permits reading and writing individual bytes or small blocks of data ▪ Small size makes it useful in portable devices such as USB “thumb drives”, digital cameras, cell phones, music players

338
Q

,

what is the Flash Memory immune to ?

A

▪ Relatively immune to physical shocks

339
Q

,

what is limitations of using Flash memory?

A

▪ Generates little heat or noise

340
Q

,

Disk Layouts – CAV vs. CLV

A

▪ CAV – Constant Angular Velocity ▪ Number of bits on each track is the same! Denser towards the center. ▪ Spins the same speed for every track

341
Q

,

Disk Layouts – CAV vs. CLV

A

▪ CLV – Constant Linear Velocity ▪ All tracks have the same physical length and number of bits ▪ Constant speed reading data off a track ▪ Drive has to speed up when accessing close to the center of the drive and slow down when accessing towards the edge of the drive

342
Q

,

Disk Layout – Multiple Zone Multiple zone recording

A

▪ Multiple zone recording ▪ Also known as zone bit recording (ZBR) or zone- CAV recording (Z-CAV) ▪ Compromise between CAV and CLV ▪ Disk divided into zones ▪ Cylinders in different zones have a different number of sectors ▪ Number of sectors in a particular zone is constant ▪ Data is buffered so the data rate to the I/O interface is constant

343
Q

,

Multiple-Zone Disk Configuration

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagegdh9qx-14A5F4717B3088D7225.png

344
Q

,

types of the Magnetic Disks

A

* Track – circle * Cylinder – same track on all platters * Block – small arc of a track * Sector – pie-shaped part of a platter * Head – reads data off the disk as disk rotates at high speed (4200-14000 RPM)

345
Q

,

A Hard Disk Layout

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image7y02qx-14A5F4854A14637D5FD.png

346
Q

,

A Hard Disk Layout

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagevxn7qx-14A5F48A6DA69D8AA6C.png

347
Q

,

Average seek time: ? how to Locate a Block of Data

A

time requied to move from one track to another

348
Q

,

Latency:

A

time required for disk to rotate to beginning of correct sector

349
Q

,

Transfer time:

A

time required to transfer a block of data to the disk controller buffer

350
Q

,

Average Seek time

A

average time to move from one track to another

351
Q

,

Average Latency time

A

▪ average time to rotate to the beginning of the sector ▪ Average Latency time = 1⁄2 * 1/rotational speed

352
Q

,

Transfer time

A

1/(# of sectors * rotational speed)

353
Q

,

Total Time to access a disk block

A

Avg. seek time + avg. latency time + avg. transfer time

354
Q

,

Magnetic Disks ▪ Data Block Format?

A

▪ Interblock gap ▪ Header ▪ Data▪ Interblock gap ▪ Header ▪ Data

355
Q

,

how ▪ Formatting disk ?

A

▪ Establishes the track positions, blocks and headers needed before use of the disk

356
Q

,

Disk Block Formats

A

Single Data Block

357
Q

,

Header for Windows disk

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image70lhrx-14A5F5096A667300041.png

358
Q

,

what is Disk Arrays?

A

Grouping of multiple disks together

359
Q

,

RAID

A

Redundant Array of Inexpensive Disks

360
Q

,

types of RAID>

A

▪ Mirrored array ▪ Striped array ▪ RAID 0 to RAID 5

361
Q

,

RAID – Mirrored is ?

A

▪ Pair of disks contain the exact same stores of data ▪ Reading data – alternate blocks of data are read from hard drives and combined

362
Q

,

how is acess time is reduced inRAID – Mirrored ?

A

Access time is reduced by approximately a factor equal to the number of disk drives in array

363
Q

,

what is Read failure RAID mirrored ?

A

block is marked and then read from the mirrored drive When using three or more mirrored drives, majority logic is used in the event of a failure. Fault-tolerant computers use this technique.

364
Q

,

what is the raid striped ?

A

▪ A file segment is stored divided into blocks on different disks ▪ Minimum of three drives needed because one disk drive is reserved for error checking

365
Q

,

writers in RAID - Striped is ?

A

block of parity words from each block of data is created and put on the reserved error checking disk

366
Q

,

what is the readers RAID - Striped?

A

parity data is used to check original data

367
Q

,

what does RAID levels ?

A

▪ RAID 0 – not true RAID, no error checking or redundancy, but data is placed across all drives for increased speed ▪ RAID 1 – mirrored array ▪ RAID 2, 3, 4 – arrays that are striped in different ways ▪ RAID 5 – error checking blocks are spread across all drives

368
Q

,

how Optical Storage ?

A

Reflected light off a mirrored or pitted surface

369
Q

,

CD rom for the optical storage ?

A

CD-ROM ▪ 650 MB of data, approximately 550 MB after formatting and error checking ▪ Spiral 3 miles long, containing 15 billion bits!

370
Q

,

what does CLV for optical storage do ?

A

▪ CLV – all blocks are same physical length ▪ Block – 2352 bytes 2k of data (2048 bytes) 16 bytes for header (12 start, 4 id) 288 bytes for advanced error control

371
Q

,

DVD – similar technology to CD-ROM

A

DID you know

372
Q

,

WORM

A

write-once read-many

373
Q

,

Optical Storage types ?

A

▪ Laser strikes land: light reflected into detector ▪ Laser strikes a pit: light scattered

374
Q

,

Layout: CD-ROM vs. Standard Disk

A

CD-ROM

375
Q

,

Layout: CD-ROM vs. Standard Disk

A

Hard Disk

376
Q

,

Types of Optical Storage

A

WORM Disks Medium-powered laser blister technology also used for

377
Q

,

Medium-powered laser blister technology also used for what ?

A

▪ CD-R, DVD-R, DVD-R, DVD+R ▪ CD-RW, DVD-RW, DVD+RW, DVD-RAM, DVD+RAMBD-RE

378
Q

,

what are the issues for Types of Optical Storage

A

▪ File compatibility issues between the different CD, DVD and WORM formats

379
Q

,

talk about magnetic tape ?

A
  1. Offline storage 2. Archival purposes 3. Disaster recovery 4. Tape Cartridges
380
Q

,

what are Tape Cartridges

A

▪ Linear tape open format vs. helical scan tape format

381
Q

,

Displays: Pixel

A

picture element

382
Q

,

Screen Size

A

diagonal length of screen

383
Q

,

Aspect ratio

A

X pixels to Y pixels ▪ 4:3 – older displays ▪ 16:9 – widescreen displays

384
Q

,

Pixel color is determined by ?

A

Pixel color is determined by intensity of 3 colors – Red, Green and Blue (RGB)

385
Q

,

True Color what is it ?

A

8 bits for each color ▪ 256 levels of intensity for each color ▪ 256 * 256 * 256 = 16.7 million colors

386
Q

,

what is resolution ?examples

A

Resolution ▪ Measured as either number of pixels per inch or size of an individual pixel ▪ Screen resolution examples: 768 x 1024 1440 x 900 1920 x 1080

387
Q

,

what is the Picture size calculation?

A

▪ Resolution * bits required to represent number of colors in picture ▪ Example: resolution is 100 pixels by 50 pixels, 4 bits required for a 16 color image 100 * 50 * 4 bits = 20,000 bits

388
Q

,

Video memory requirements are,,,,,,,,,

A

significant!

389
Q

,

Interlaced vs. Progressive Scan diagram ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagem9jzqx-14A60C6B35C39AA9222.png

390
Q

,

Diagram of Raster Screen Generation Process

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageqqucrx-14A60C70EE0065869CC.png

391
Q

,

Color Transformation Table

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagen681qx-14A60C7715C29E8AB2E.png

392
Q

,

Display Example diagram ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagejcy0qx-14A60C7CF9A2957E1E9.png

393
Q

,

LCD – Liquid Crystal Display known as ?

A

Fluorescent light or LED panel

394
Q

,

how many colors in the LCD?

A

3 color cells per pixel

395
Q

,

Operation of the LCD

A

1 st filter polarizes light in a specific direction ▪ Electric charge rotates molecules in liquid crystal cells proportional to the strength of colors ▪ Color filters only let through red, green, and blue light ▪ Final filter lets through the brightness of light proportional to the polarization twist

396
Q

,

LCDs (continued) what types of matrices ?

A

▪ Active matrix ▪ One transistor per cell ▪ More expensive ▪ Brighter picture ▪ Passive matrix ▪ One transistor per row or column ▪ Each cell is lit in succession ▪ Display is dimmer since pixels are lit less frequently

397
Q

,

CRT Display Technology

A
  1. CRTs (similar to TVs) 2. 3 stripes of phosphors for each color 3. 3 separate electron guns for each color 4. Strength of beam → brightness of color 5. Raster scan * 30x per second * Interlaced vs. non-interlaced (progressive scan)
398
Q

,

OLED Display Technology traits ?

A

No backlight Consists of red, green and blue LEDs Each LED lights up individually Very thin displays with panels less than 3mm thick!

399
Q

,

Printers comapsion between dots vs pixels ?

A

▪ Dots vs. pixels ▪ 300-2400 dpi vs. 70-100 pixels per inch ▪ Dots are on or off, pixels have intensities

400
Q

,

types of printers ?

A
  1. Typewriter / Daisy wheels – obsolete 2. Impact printing - dot matrix – mostly obsolete 3. Inkjet – squirts heated droplets of ink 4. Laser printer 5. Thermal wax transfer 6. Dye Sublimation
401
Q

,

Creating a Gray Scale how diagram ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageyr50qx-14A60CE89856F80B0FC.png

402
Q

,

Laser Printer Operation

A
  1. Dots of laser light are beamed onto a drum 2. Drum becomes electrically charged 3. Drum passes through toner which then sticks to the electrically charged places 4. Electrically charged paper is fed toward the drum 5. Toner is transferred from the drum to the paper
403
Q

,

Laser Printer Operation (cont)

A
  1. The fusing system heats and melts the toner onto the paper 7.A corona wire resets the electrical charge on the drum
404
Q

,

Laser Printer Operation

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagewvqgrx-14A60D1DAF72B87B9F6.png

405
Q

,

Laser Printer Operation (cONT)

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageez72qx-14A60D23E8A3FD1D530.png

406
Q

,

what other Computer Peripherals?

A

* Scanners ▪ Flatbed, sheet-fed, hand-held ▪ Light is reflected off the sheet of paper ▪ User Input Devices ▪ Keyboard, mouse, light pens, graphics tablets ▪ Communication Devices ▪ Telephone modems ▪ Network devices

407
Q

,

Network Communication Devices is just ?

A

▪ Network is just another I/O device ▪ Network I/O controller is the network interface card (NIC)

408
Q

,

types of networking connection ?

A

▪ Ethernet, FDDI fiber, token-ring

409
Q

,

Medium access control (MAC) protocols what does it define ?

A

Define the specific rules of communication for the network

410
Q

,

Storage Hierarchy

A

– Performance is driven by latency and bandwidth. – The more layers away from the CPU . . . – . . . the higher the latency – . . . the larger the capacity

411
Q

,

Storage Hierarchy

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_193-14A60DB3ABF2FB371BE.png

412
Q

,

Storage Hierarchy 2

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_193-14A60DB6F9B5D5FCC87.png

413
Q

,

Magnetic Disk Technology – Terminology Platter?

A

a spinning disc within a drive, made of glass or aluminum, and coated with magnetic media

414
Q

,

Magnetic Disk Technology – Terminology Head:

A

floats above the media, reading or writing the magnetically encoded data

415
Q

,

Magnetic Disk Technology – Terminology track?

A

a ring on a single platter

416
Q

,

Magnetic Disk Technology – Terminology Cylinder?

A

a track across all platters

417
Q

,

Magnetic Disk Technology – Terminology sector?

A

a wedge shaped slice of a platter

418
Q

,

Block in the Magnetic disk terminology

A

the intersection of a track and a sector

419
Q

,

CAV (constant angular velocity):

A

used by HDD; disk always spins at the same speed. Problem: wastes space on the outer rings

420
Q

,

– CLV (constant linear velocity):

A

The number of bits passing under the head is constant. Faster angular velocity at the inner tracks; slower on the outer

421
Q

,

Raid: most Disks fail why ?

A

Disks often fail because they are at least partly mechanical. RAID (redundant array of independent disks) attempts to improve redundancy and bandwidth

422
Q

,

Raid combine 3 functions?

A

– Combine three primary functions: – Mirroring – Striping – Parity checks

423
Q

,

RAID 0: Striping D?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageaqe2qx-14A60E13B8531F798C4.png

424
Q

,

RAID 1: Mirroring D?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image4x7drx-14A60E1990236841F31.png

425
Q

,

RAID 5: Striping with distributed parity D?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageywpbrx-14A60E1EFC62DB94602.png

426
Q

,

– RAID 10: Stripe across mirrors D?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagelpzgrx-14A60E254722BA1C6BF.png

427
Q

,

what does Memory hierarchy show ?

A

Memory hierarchy shows the inverse relationship between speed and capacity in computing systems.

428
Q

,

– Magnetic disks have several kinds of latency:?

A

seek time, rotational delay, and transfer time.

429
Q

,

how RAID try and fix ?

A

RAID attempts to compensate for latency and failures by employing striping, mirroring, and parity checks.

430
Q

,

Basic Model of Processing speed or program execution

A

determined primarily by ability of I/O operations to stay ahead of processor.

431
Q

,

I/O Requirements

A

▪ Means for addressing different peripheral devices ▪ A way for peripheral devices to initiate communication with the CPU ▪ An efficient means of transferring data directly between I/O and memory for large data transfers since programmed I/O is suitable only for slow devices and individual word transfers

432
Q

,

I/O Requirements

A

▪ Buses that interconnect high-speed I/O devices with the computer must support high data transfer rates ▪ Means for handling devices with extremely different control requirements

433
Q

,

I/O Interfaces Are necessary because of ?

A

▪ Different formats required by the devices ▪ Incompatibilities in speed between the devices and the CPU make synchronization difficult ▪ Bursts of data vs. streaming data ▪ Device control requirements that would tie up too much CPU time

434
Q

,

Examples of I/O Devices

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageelpzqx-14A617862FA12878A03.png

435
Q

,

Simple I/O Configuration D?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image77u8qx-14A61DE34A91D5DD827.png

436
Q

,

More Complex I/O Module

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imager61jrx-14A61DDE2410D2FE1D4.png

437
Q

,

Advanced I/O Techniques

A

▪ Programmed I/O ▪ CPU controlled I/O ▪ Interrupt Driven I/O ▪ External input controls ▪ Direct Memory Access Controllers ▪ Method for transferring data between main memory and a device that bypasses the CPU

438
Q

,

Programmed I/O traits ?

A

I/O data and address registers in CPU ▪ One word transfer per I/O instruction ▪ Address information for each I/O device ▪ LMC I/O capability for 100 devices ▪ Full instruction fetch/execute cycle

439
Q

,

where is programmed I/O used ?

A

▪ Primary use: ▪ keyboards ▪ communication with I/O modules (see DMA)

440
Q

,

Programmed I/O Example

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageqqw8qx-14A617B1C6C30C28BFD.png

441
Q

,

Programmed I/O Example

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image3oq4qx-14A617B679E34F0849B.png

442
Q

,

Interrupt Terminology ▪ Interrupt lines (hardware

A

▪ One or more special control lines to the CPU

443
Q

,

Interrupt request

A

dont know

444
Q

,

▪ Interrupt handlers

A

▪ Program that services the interrupt ▪ Also known as an interrupt routine or device driver

445
Q

,

▪ Context of interrupts

A

▪ Saved registers of a program before control is transferred to the interrupt handler ▪ Allows program to resume exactly where it left off when control returns to interrupted program

446
Q

,

Use of Interrupts ?

A

▪ Notify that an external event has occurred ▪ real-time or time-sensitive ▪ Signal completion ▪ printer ready or buffer full ▪ Allocate CPU time ▪ time sharing ▪ Indicate abnormal event (CPU originates for notification and recovery) ▪ illegal operation, hardware error ▪ Software interrupts

447
Q

,

The CPU - The Interrupt Cycle how ?D

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_220-14A617DC32A55AC6970.png

448
Q

,

Servicing the Interrupt

A
  1. Lower priority interrupts are held until higher priority interrupts are complete 2. Suspend program in progress 3. Save context, including last instruction executed and data values in registers, in the PCB or the stack area in memory 4. Branch to interrupt handler progra
449
Q

,

Servicing an Interrupt

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagefprjrx-14A617E93147EADFB7D.png

450
Q

,

what are Interrupt Processing Methods?

A

1.Vectored interrupt ▪ Address of interrupting device is included in the interrupt ▪ Requires additional hardware to implement 2.▪ Polling ▪ Identifies interrupting device by polling each device ▪ General interrupt is shared by all devices

451
Q

,

Vectored Interrupts

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagel8jzqx-14A6180E5F022506E5A.png

452
Q

,

Polled Interrupts

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image3rserx-14A618128902A20A81B.png

453
Q

,

Print Handler Interrupt

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagenyvyqx-14A61DF1902346C64BB.png

454
Q

,

Using an Interrupt for Time Sharing

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagevwbkrx-14A6181D25060221D4B.png

455
Q

,

Multiple Interrupts Example

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imaged1nyqx-14A61DFB4C90E1A1FE0.png

456
Q

,

how is Direct Memory Access happen ?

A
  1. Transferring large blocks of data 2. Direct transfer to and from memory 3. CPU not actively involved in transfer itself
457
Q

,

Required conditions for DMA ?

A

▪ The I/O interface and memory must be connected ▪ The I/O module must be capable of reading and writing to memory ▪ Conflicts between the CPU and the I/O module must be avoided ▪ Interrupt required for completion

458
Q

,

DMA Instructions

A

Application program requests I/O service from operating system privileged programmed I/O instructions

459
Q

,

To initiate DMA, programmed I/O is used to send the following information:

A
  1. location of data on I/O device 2. the starting location in memory 3. the size of the block 4. read/write
460
Q

,

when Interrupt to CPU in DMA?

A

Interrupt to CPU upon completion of DMA

461
Q

,

DMA Initiation and Control

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagep4aarx-14A6185B9AE2C403B9B.png

462
Q

,

I/O Module Interfaces

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imaget54erx-14A6185FE06671AB35A.png

463
Q

,

I/O Module Functions

A

▪ Recognizes messages from device(s) addressed to it and accepts commands from the CPU ▪ Provides a buffer where the data from memory can be held until it can be transferred to the device ▪ Provides the necessary registers and controls to perform a direct memory transfer ▪ Physically controls the device ▪ Copies data from its buffer to the device/from the CPU to its buffer ▪ Communicates with CPU

464
Q

,

Input/Output Characteristics

A

– Many orders of magnitude slower than memory – Character vs. block based – Burst vs. steady transfers

465
Q

,

Three approaches to I/O

A

– Programmed – Interrupt-driven – Direct memory acces

466
Q

,

Programmed I/O

A

– CPU is responsible for reading/writing to devices – Special “input” instruction on CPU – I/O data register and I/O address register – Each device is assigned a unique address.

467
Q

,

Programmed I/O types

A

– Memory mapped I/O alternative – Treat the I/O device as a memory address for reads and writes. Simplifies programmer interface; slightly more complicated control circuitry. – Problems with all programmed I/O – Must check status bits to see if I/O is “ready.” – Use a polling loop (busy-wait) to send and receive data to devices.

468
Q

,

Interrupts

A

– Busy-waits (polling) wastes resources but has simpler hardware. – Alternative: After an I/O request from the CPU, let the I/O device notify the CPU when data is ready to be read (called an interrupt)

469
Q

,

Alternative: After an I/O request from the CPU, let the I/O device notify the CPU when data is ready to be read (called an interrupt).

A

Each device is assigned an IRQ line (signal). I/O controller sets IRQ line status high. CPU detects IRQ at beginning of fetch/execute. CPU saves state of running program and switches to an IRQ handler routine. Routine services the request. Control is returned to the previously running code

470
Q

,

Problems with interrupt driven I/O

A

CPU still involved with each interrupt – Only transfers a single byte/word

471
Q

,

did you know Only transfers a single byte/word

A

Disk or network transfers may be hundreds or thousands of bytes. IRQ handler code may be hundreds of instructions. Still too much overhead.

472
Q

,

DMA

A

– Direct Memory Access (DMA) – Add a specialized kind of CPU that can directly transfer data from device to memory.

473
Q

,

Purely programmed I/O requires special I/O instructions,

A

, I/O data and address registers, and polling loops that waste CPU resources.

474
Q

,

Interrupt-driven I/O avoids

A

busy-waiting but is unsuitable for large block transfers due to interrupt handler execution overhead.

475
Q

,

DMA combines PIO and IRQ handlers

A

with a special controller to transfer large amounts of block data efficiently directly to memory.

476
Q

,

▪ Current CPU Architecture Designs:

A

▪ Traditional modern architectures ▪ VLIW (Transmeta) – Very Long Instruction Word ▪ EPIC (Intel) – Explicitly Parallel Instruction Computer

477
Q

,

Current CPU Architectures:

A

* IBM Mainframe series * Intel x86 family * IBM POWER/PowerPC family * Sun SPARC family

478
Q

,

Problems with early CPU Architectures and solutions:

A

▪ Large number of specialized instructions were rarely used but added hardware complexity and slowed down other instructions ▪ Slow data memory accesses could be reduced by increasing the number of general purpose registers ▪ Using general registers to hold addresses could reduce the number of addressing modes and simplify architecture design

479
Q

,

Problems with early CPU Architectures and solutions:

A

▪ Fixed-length, fixed format instruction words would allow instructions to be fetched and decoded independently and in parallel

480
Q

,

how VLIW Architecture?

A

▪ Transmeta Crusoe CPU ▪ 128-bit instruction bundle = molecule ▪ Four 32-bit atoms (atom = instruction) ▪ Parallel processing of 4 instructions ▪ 64 general purpose registers ▪ Code morphing layer ▪ Translates instructions written for other CPUs into molecules ▪ Instructions are not written directly for the Crusoe CPU

481
Q

,

EPIC Architecture

A

▪ 128-bit instruction bundle ▪ 3 41-bit instructions ▪ 5 bits to identify type of instructions in bundle * 128 64-bit general purpose registers * 128 82-bit floating point registers * Intel X86 instruction set included * Programmers and compilers follow guidelines to ensure parallel execution of instructions

482
Q

,

Fetch-Execute Cycle Timing Issues?

A

▪ Computer clock is used for timing purposes for each step of the instruction cycle ▪ GHz (gighertz) – billion steps per second ▪ Instructions can (and often) take more than one step ▪ Data word width can require multiple steps

483
Q

,

CPU Features and Enhancements

A

Separate Fetch/Execute Units Pipelining Multiple, Parallel Execution Units Scalar Processing Superscalar Processing Branch Instruction Processing

484
Q

,

what include fetch unit ?

A

▪ Instruction fetch unit ▪ Instruction decode unit Determine opcode Identify type of instruction and operands ▪ Several instructions are fetched in parallel and held in a buffer until decoded and executed ▪ IP – Instruction Pointer register holds instruction location of current being processed

485
Q

,

what include Execute Unit?

A

▪ Receives instructions from the decode unit ▪ Appropriate execution unit services the instruction

486
Q

,

Instruction Pipelining

A

▪ Assembly-line technique to allow overlapping between fetch-execute cycles of sequences of instructions

487
Q

,

Scalar processing

A

Average instruction execution is approximately equal to the clock speed of the CPU

488
Q

,

Problems from stalling

A

Instructions have different numbers of steps

489
Q

,

Problems from branching

A

did you know piplining has that problem

490
Q

,

Branch Problem Solutions

A

▪ Separate pipelines for both possibilities ▪ Probabilistic approach ▪ Requiring the following instruction to not be dependent on the branch ▪ Instruction Reordering (superscalar processing)

491
Q

,

Multiple, Parallel Execution Units what is it ?

A

▪ Different instructions have different numbers of steps in their cycle ▪ Differences in each step ▪ Each execution unit is optimized for one general type of instruction ▪ Multiple execution units permit simultaneous execution of several instructions

492
Q

,

Superscalar Processing

A

▪ Process more than one instruction per clock cycle ▪ Separate fetch and execute cycles as much as possible ▪ Buffers for fetch and decode phases ▪ Parallel execution units

493
Q

,

Superscalar Issues

A

▪ Out-of-order processing – dependencies (hazards) ▪ Data dependencies ▪ Branch (flow) dependencies and speculative execution ▪ Parallel speculative execution or branch prediction ▪ Branch History Table ▪ Register access conflicts ▪ Rename or logical registers

494
Q

,

Memory Enhancements

A

▪ Memory is slow compared to CPU processing speeds ! ▪ 2Ghz CPU = 1 cycle in 1⁄2 of a billionth of a second ▪ 70ns DRAM = 1 access in 70 millionth of a second ▪ Methods to improvement memory accesses ▪ Wide Path Memory Access • Retrieve multiple bytes instead of 1 byte at a time

495
Q

,

Memory Enhancements

A

▪ Memory Interleaving • Partition memory into subsections, each with its own address register and data register ▪ Cache Memory

496
Q

,

Cache Memory

A

▪ Blocks: 8 or 16 bytes ▪ Tags: pointer to location in main memory ▪ Cache controller ▪ hardware that checks tags ▪ Cache Line ▪ Unit of transfer between storage and cache memory ▪ Hit Ratio: ratio of hits out of total requests ▪ Synchronizing cache and memory ▪ Write through ▪ Write back

497
Q

,

Step-by-Step Use of Cache1

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image102irx-14A61BF6090502EDC27.png

498
Q

,

Performance Advantages of cache memory?

A

▪ Hit ratios of 90% common ▪ 50%+ improved execution speed ▪ Locality of reference is why caching works ▪ Most memory references confined to small region of memory at any given time ▪ Well-written program in small loop, procedure or function ▪ Data likely in array ▪ Variables stored togeth

499
Q

,

Why do the sizes of the caches have to be different?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagedbqyqx-14A61C1020362FF5298.png

500
Q

,

reasons for Multiprocessing

A

▪ Reasons ▪ Increase the processing power of a system ▪ Parallel processing

501
Q

,

Multiprocessor system in Multiprocessing is ?

A

▪ Tightly coupled ▪ Multicore processors - when CPUs are on a single integrated circuit

502
Q

,

what is Multiprocessor Systems for ?

A

▪ Identical access to programs, data, shared memory, I/O, etc. ▪ Easily extends multi-tasking, and redundant program executio

503
Q

,

▪ Two ways to configure Multiprocessor Systems

A

▪ Two ways to configure ▪ Master-slave multiprocessing ▪ Symmetrical multiprocessing (SMP)

504
Q

,

Master-Slave Multiprocessing, Master CPU

A

▪ Manages the system ▪ Controls all resources and scheduling ▪ Assigns tasks to slave CPUs

505
Q

,

aAdvantages of Master-Slave Multiprocessing?

A

Advantages ▪ Simplicity ▪ Protection of system and data

506
Q

,

▪ Disadvantages of Master-Slave Multiprocessing?

A

▪ Disadvantages ▪ Master CPU becomes a bottleneck ▪ Reliability issues – if master CPU fails entire system fails

507
Q

,

Symmetrical Multiprocessing

A

▪ Each CPU has equal access to resources ▪ Each CPU determines what to run using a standard algorithm

508
Q

,

▪ Disadvantages of Symmetrical Multiprocessing

A

▪ Resource conflicts – memory, i/o, etc. ▪ Complex implementation

509
Q

,

Advantages Symmetrical Multiprocessing ?

A

▪ High reliability ▪ Fault tolerant support is straightforward ▪ Balanced workload

510
Q

,

General Enhancements – Use RISC-based techniques

A

– Fewer instruction formats, fixed-length → faster decoding – More general purpose registers → fewer memory accesses

511
Q

,

Clock cycle and instruction cycle

A

– Most instructions take several clock cycles to execute: Fetch the new instruction [IF]. Decode the instruction [ID]. Execute the instruction [EX]. Access memory (if needed) [MEM]. Write back to the registers [WB]

512
Q

,

Each stage takes a clock cycle, so complete execution takes 5 cycles. Can we do better?

A

Waiting for all five stages of instruction execution to complete is like building something from start to finish

513
Q

,

Clock cycle and instruction cycle Or can the CPU overlap the execution of several instructions at once because they’re all similar?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_221-14A61CABCA1789F393E.png

514
Q

,

– Five stages of instruction execution

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagekqh5qx-14A61CB0B744AF6B2F4.png

515
Q

,

Five stages of instruction execution

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_222-14A61CB7A5758786932.png

516
Q

,

Clock cycle and instruction cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_223-14A61CBF1695639B190.png

517
Q

,

– Problems with pipelining

A

Dependencies (register interlock)—if an instruction needs a result from the immediately preceding instruction, that result won’t be written back until WB, but the result is needed in EX.

518
Q

,

Problems with pipelining

A

– Branching—when the instruction being executed is a branch, we can’t know if the branch will be taken until after stage 3. But by that time, other instructions are “in flight.”

519
Q

,

Clock cycle and instruction cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_226-14A61CDF94829EB48ED.png

520
Q

,

Superscalar Processing

A

RISC and pipelining lets each functional unit in a CPU be fully utilized all of the time. – But, what if there were multiple ALUs or multiple decoders? Then multiple instructions could be executed at once. – Prerequisite: Multiple instructions should be fetched at once via a large path to memory.

521
Q

,

Superscalar Processing D

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_227-14A61CEE5785DB511F3.png

522
Q

,

Superscalar Processing DD

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_228-14A61CF64A8699CC04A.png

523
Q

,

– Problems with superscalar processing

A

– Same general categories as with pipelining: dependencies and branches – Except now forwards, stalls, or canceling may need to be between several functional units! – CPUs become very complex again, yet it is common to have 2 to 4 separate pipelines per core in modern processors.

524
Q

,

Did you know 1

A

RISC-based CPUs offer general performance enhancements due to simplified formats and single-clock cycle execution.

525
Q

,

Pipelining allows…..

A

multiple instructions to be in various stages of execution at once.

526
Q

,

Superscalar processing duplicates……

A

pipelines in a single core to have multiple instructions executing simultaneously.

527
Q

,

Data dependencies and branches are……?

A

hazards to both pipelining and superscalar architectures.

528
Q

,

Recall CPU Pipelining

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_229-14A61D305A2321FEE0C.png

529
Q

,

Three complementary approaches memory ?

A

All three are used simultaneously in the system design

530
Q

,

Wide path memory access

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_231-14A61D4F7AD5DBD3F51.png

531
Q

,

Wide path memory access 1

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_232-14A61E16BE55635A342.png

532
Q

,

Wide path memory access 2

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_233-14A61E211B84B36A4AF.png

533
Q

,

Wide path memory access

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_234-14A61E290734D580E81.png

534
Q

,

Memory interleaving

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_235-14A61E356D54EB3628B.png

535
Q

,

Memory interleaving D

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagesgm2qx-14A61E3B32D3AF72413.png

536
Q

,

Cache Memory

A

Use a small amount of expensive SRAM as a buffer against the large amount of DRAM

537
Q

,

Cache Memory

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagekfh3qx-14A61E51C745DDD5B10.png

538
Q

,

Cache Memory

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_237-14A61E5ABA96F16AC1E.png

539
Q

,

cache entries consists of ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_238-14A61E64D2943E88C7F.png

540
Q

,

cache replacement algorithm ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_239-14A61E6D6156AC4FB57.png

541
Q

,

cache memory what should happen on memory write ?

A

Cache coherency gets particularly tricky with multiple cores and multiple levels of cache.

542
Q

,

DID you know

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_241-14A61E86E6900A46784.png

543
Q

,

Domain Names

A

▪ Hierarchical system of network address identifiers used throughout the Internet and on local area networks, intranets and extranets ▪ Created so users would not have to memorize IP addresses

544
Q

,

what is the Domain name resolution ?

A

translates domain names into IP addresses

545
Q

,

what does DNS Domain Name System do ?

A

▪ Uses a massive distributed database containing a directory system of servers ▪ Each entry contains a domain name and an associated IP addres

546
Q

,

Domain Name System (DNS) diagram

A

DNS Server Hierarchy

547
Q

,

The Elements of a Domain Name

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image0d15qx-14A5D855D3943736A35.png

548
Q

,

Top Domain Name Registrations

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagem8ucrx-14A5D85DCEF1F3BC2A2.png

549
Q

,

Domain Name Resolution diagram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagegfh0qx-14A5D8663DA589825FD.png

550
Q

,

what is DOEs Transport Layer ▪ TCP protocol?

A

▪ TCP protocol ▪ Sends a packet to TCP at the destination site, requesting a connection ▪ Handshaking – back and forth series of requests and acknowledgments

551
Q

,

▪ If handshaking negotiations are successful in the transport layer ?

A

▪ If handshaking negotiations are successful, a connection is opened ▪ Connection is logically full-duplex

552
Q

,

Three-Way TCP Connection Handshake Diagram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagegq72qx-14A7DE018793E0C9E3C.png

553
Q

,

TCP Segment Format Diagram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image60rarx-14A5D8887C73EA6AD07.png

554
Q

,

Network Layer IP protocol?

A

▪ IP protocol ▪ Responsible for relaying packets from the source end node to the destination end node through intermediate nodes ▪ Performed using datagram packet switching and logical IP addresses ▪ Best-attempt unreliable service ▪ Size of datagram ranges from 20 to 65,536 bytes ▪ Header size between 20 and 60 bytes

555
Q

,

IPv4 Addresses

A

▪ Registered and allocated by ICANN ▪ 32 bits long divided into 4 octets ▪ Assigned in blocks of contiguous addresses ▪ Number of addresses is a power of two

556
Q

,

IPv4 Addresses ▪ Divided into three levels?

A

▪ Network address ▪ Subnetworks (subnets) ▪ Hosts (nodes)

557
Q

,

what does Masks do ?

A

▪ Used to separate the different parts of the address

558
Q

,

IPv4 Datagram Format Diagram ?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageolsfrx-14A5D8C03356DFD1F0F.png

559
Q

,

IP Addresses Diagram ?

A

IP Block Addresses

560
Q

,

IP Addresses IP Hierarchy and Subnet Mask Diagram ?

A

IP Hierarchy and Subnet Mask

561
Q

,

Reseved IP Addresses

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagecoc0qx-14A5D8DF1212D3B10F3.png

562
Q

,

Two methods to distribute IP addresses more efficiently:?

A
  1. Use of private network IP addresses behind a router 2. Dynamic Host Configuration Protocol (DHCP)
563
Q

,

what does Dynamic Host Configuration Protocol (DHCP) do ?

A

Maintain a bank of available IP addresses and assign them dynamically to computers for use when the computers are attached to the network Method often used by large organizations, DSL and cable providers

564
Q

,

what does DHCP Client and server ?

A

* DHCP client on computer or network device broadcasts a query to locate the DHCP server * DHCP server responds with a lease which includes an IP address, domain name of network, IP address of DNS server, subnet mask, IP address of gateway and other configuration parameters

565
Q

,

Operation of IP two major functions?

A
  1. ▪ Routes datagrams from node to node until they reach their destination node 2. ▪ Translates IP addresses to physical addresses before it passes the packets to the data link later for delivery
566
Q

,

(ARP)

A

Address Resolution Protocol

567
Q

,

when is the (ARP) network implemented ?

A

▪ Implemented at the network layer

568
Q

,

what does ARP do ?

A

▪ Translation of IP address to physical address at each intermediate node until destination is reached ▪ A broadcast of the IP address is sent to every node on the network. The matching node responds with a physical address ▪ Physical address (MAC address in the case of Ethernet) is sent in frame to the data link layer At final destination, the packet is passed up to the transport layer for deployment to the application layer

569
Q

,

Data Link Layer what is this responsible for ?

A

Layer responsible for transmitting a packet from one node to the next node

570
Q

,

how is node access defined ?

A

Node access defined by the medium access control (MAC) protocol ▪ Steer data to its destination ▪ Detect errors ▪ Prevent collisions

571
Q

,

what does Ethernet (CSMA-CD)?

A

▪ Predominant medium-access protocol for local area networks ▪ Standard Ethernet packet is a frame (see next slide)

572
Q

,

Ethernet Frame

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagetjz1qx-14A5D9CF97736E01D1D.png

573
Q

,

Hub-Based Ethernet

A

* Simple means of wiring bussed Ethernet together * Logically still a bus network * CSMA-CD

574
Q

,

when does the collision happens in the hub- based Ethernet happen ?

A

Collision ▪ Occurs when multiple nodes access the network in such a way that their messages become mixed and garbled

575
Q

,

what is Network propagation delay ?

A

Amount of time that it takes for one packet to get from one end of the network to the other

576
Q

,

when is gthe hub based Etherent work ?

A

▪ Adequate for networks with light traffic

577
Q

,

what Switched Ethernet do ?

A
  1. Permits point-to-point connection of any pair of nodes 2. Multiple pairs can be connected simultaneously 3. Possible to connect nodes in full-duplex mode 4. Each pair of connections operates at the maximum bit rate of the network
578
Q

,

(QoS)

A

Quality of Service

579
Q

,

wh/at does QOS do

A

. 1. Methods to reserve and prioritize channel capacity to favor packets that require special treatment 2. Service guarantees from contract carrier services that specify particular levels of throughput, delay and jitter

580
Q

,

Jitter

A

variation in delay from packet to packet

581
Q

,

Differentiated service (DiffServ) about

A
  1. ▪ 8-bit (DS) field in IP header 2. ▪ Set by the application at the sender or by the first node 3. ▪ Diffserv capable nodes such as routers can then prioritize and route packets based on the packet class
582
Q

,

Network Security Categories

A
  1. Intrusion 2. Confidentiality 3. Authentication 4. Data integrity and non-repudiation 5. Assuring network availability and access control
583
Q

,

Intrusion

A

Keeping network and system resources free from intruders

584
Q

,

Confidentiality

A

Keeping the content of data private

585
Q

,

Authentication

A

Verifying the identity of a source of data being received

586
Q

,

Data integrity and non-repudiation

A

Protecting the content of data communication against changes and verifying the source of the message

587
Q

,

Assuring network availability and access control

A

Keep network resources operational and restricting access to those permitted to use them

588
Q

,

▪ Network intrusions how /

A

▪ Packet sniffers read data in a packet as it passes through a network ▪ Probing attacks to uncover IP address / port numbers that accept data packets

589
Q

,

what are Physical and Logical Restriction ?

A

Physical and Logical Restriction ▪ Limit access to wiring and network equipment ▪ Firewall ▪ Private networks

590
Q

,

Encryption

A

1-Symmetric key cryptography Both key used for encryption and decryption Both sender and receiver use the same key which makes security difficult 2- Public key cryptography Two different keys are used for encryption and decryption

591
Q

,

MPLS

A

(Multi-Protocol Label Switching) Creates a virtual circuit over packet switched networks to improve forwarding speed of datagrams

592
Q

,

ATM

A

(Asynchronous Transfer Mode) ▪ Partial-mesh network technology in which data passes through the network in cells (53-byte packets)

593
Q

,

SONET and SDH

A

(Synchronous Optical Network) and (Synchronous Digital Hierarchy) Protocol that uses fiber optic to create wide area networks with very high bit rates over long distances

594
Q

,

Frame Relay

A

▪ Slow, wide area network standard

595
Q

,

Frame Delay

A

A standardized wide area network technology that specifies the physical and logical link layer of digital telecommunications channels using a packet switching methodology

IT110 (10 decks)

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