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IT110 > export_week 11chapter 9 input output > Flashcards

export_week 11chapter 9 input output Flashcards

1
Q

,

Basic Model of Processing speed or program execution

A

determined primarily by ability of I/O operations to stay ahead of processor.

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2
Q

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I/O Requirements

A

▪ Means for addressing different peripheral devices ▪ A way for peripheral devices to initiate communication with the CPU ▪ An efficient means of transferring data directly between I/O and memory for large data transfers since programmed I/O is suitable only for slow devices and individual word transfers

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3
Q

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I/O Requirements

A

▪ Buses that interconnect high-speed I/O devices with the computer must support high data transfer rates ▪ Means for handling devices with extremely different control requirements

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4
Q

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I/O Interfaces Are necessary because of ?

A

▪ Different formats required by the devices ▪ Incompatibilities in speed between the devices and the CPU make synchronization difficult ▪ Bursts of data vs. streaming data ▪ Device control requirements that would tie up too much CPU time

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5
Q

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Examples of I/O Devices

A
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6
Q

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Simple I/O Configuration D?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image77u8qx-14A61DE34A91D5DD827.png

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7
Q

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More Complex I/O Module

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imager61jrx-14A61DDE2410D2FE1D4.png

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8
Q

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Advanced I/O Techniques

A

▪ Programmed I/O ▪ CPU controlled I/O ▪ Interrupt Driven I/O ▪ External input controls ▪ Direct Memory Access Controllers ▪ Method for transferring data between main memory and a device that bypasses the CPU

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9
Q

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Programmed I/O traits ?

A

I/O data and address registers in CPU ▪ One word transfer per I/O instruction ▪ Address information for each I/O device ▪ LMC I/O capability for 100 devices ▪ Full instruction fetch/execute cycle

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10
Q

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where is programmed I/O used ?

A

▪ Primary use: ▪ keyboards ▪ communication with I/O modules (see DMA)

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11
Q

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Programmed I/O Example

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageqqw8qx-14A617B1C6C30C28BFD.png

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12
Q

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Programmed I/O Example

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image3oq4qx-14A617B679E34F0849B.png

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13
Q

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Interrupt Terminology ▪ Interrupt lines (hardware

A

▪ One or more special control lines to the CPU

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14
Q

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Interrupt request

A

dont know

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15
Q

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▪ Interrupt handlers

A

▪ Program that services the interrupt ▪ Also known as an interrupt routine or device driver

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16
Q

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▪ Context of interrupts

A

▪ Saved registers of a program before control is transferred to the interrupt handler ▪ Allows program to resume exactly where it left off when control returns to interrupted program

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17
Q

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Use of Interrupts ?

A

▪ Notify that an external event has occurred ▪ real-time or time-sensitive ▪ Signal completion ▪ printer ready or buffer full ▪ Allocate CPU time ▪ time sharing ▪ Indicate abnormal event (CPU originates for notification and recovery) ▪ illegal operation, hardware error ▪ Software interrupts

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18
Q

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The CPU - The Interrupt Cycle how ?D

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_220-14A617DC32A55AC6970.png

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19
Q

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Servicing the Interrupt

A
  1. Lower priority interrupts are held until higher priority interrupts are complete 2. Suspend program in progress 3. Save context, including last instruction executed and data values in registers, in the PCB or the stack area in memory 4. Branch to interrupt handler progra
20
Q

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Servicing an Interrupt

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagefprjrx-14A617E93147EADFB7D.png

21
Q

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what are Interrupt Processing Methods?

A

1.Vectored interrupt ▪ Address of interrupting device is included in the interrupt ▪ Requires additional hardware to implement 2.▪ Polling ▪ Identifies interrupting device by polling each device ▪ General interrupt is shared by all devices

22
Q

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Vectored Interrupts

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagel8jzqx-14A6180E5F022506E5A.png

23
Q

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Polled Interrupts

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image3rserx-14A618128902A20A81B.png

24
Q

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Print Handler Interrupt

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagenyvyqx-14A61DF1902346C64BB.png

25
Q

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Using an Interrupt for Time Sharing

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagevwbkrx-14A6181D25060221D4B.png

26
Q

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Multiple Interrupts Example

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imaged1nyqx-14A61DFB4C90E1A1FE0.png

27
Q

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how is Direct Memory Access happen ?

A
  1. Transferring large blocks of data 2. Direct transfer to and from memory 3. CPU not actively involved in transfer itself
28
Q

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Required conditions for DMA ?

A

▪ The I/O interface and memory must be connected ▪ The I/O module must be capable of reading and writing to memory ▪ Conflicts between the CPU and the I/O module must be avoided ▪ Interrupt required for completion

29
Q

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DMA Instructions

A

Application program requests I/O service from operating system privileged programmed I/O instructions

30
Q

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To initiate DMA, programmed I/O is used to send the following information:

A
  1. location of data on I/O device 2. the starting location in memory 3. the size of the block 4. read/write
31
Q

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when Interrupt to CPU in DMA?

A

Interrupt to CPU upon completion of DMA

32
Q

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DMA Initiation and Control

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagep4aarx-14A6185B9AE2C403B9B.png

33
Q

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I/O Module Interfaces

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imaget54erx-14A6185FE06671AB35A.png

34
Q

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I/O Module Functions

A

▪ Recognizes messages from device(s) addressed to it and accepts commands from the CPU ▪ Provides a buffer where the data from memory can be held until it can be transferred to the device ▪ Provides the necessary registers and controls to perform a direct memory transfer ▪ Physically controls the device ▪ Copies data from its buffer to the device/from the CPU to its buffer ▪ Communicates with CPU

35
Q

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Input/Output Characteristics

A

– Many orders of magnitude slower than memory – Character vs. block based – Burst vs. steady transfers

36
Q

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Three approaches to I/O

A

– Programmed – Interrupt-driven – Direct memory acces

37
Q

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Programmed I/O

A

– CPU is responsible for reading/writing to devices – Special “input” instruction on CPU – I/O data register and I/O address register – Each device is assigned a unique address.

38
Q

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Programmed I/O types

A

– Memory mapped I/O alternative – Treat the I/O device as a memory address for reads and writes. Simplifies programmer interface; slightly more complicated control circuitry. – Problems with all programmed I/O – Must check status bits to see if I/O is “ready.” – Use a polling loop (busy-wait) to send and receive data to devices.

39
Q

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Interrupts

A

– Busy-waits (polling) wastes resources but has simpler hardware. – Alternative: After an I/O request from the CPU, let the I/O device notify the CPU when data is ready to be read (called an interrupt)

40
Q

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Alternative: After an I/O request from the CPU, let the I/O device notify the CPU when data is ready to be read (called an interrupt).

A

Each device is assigned an IRQ line (signal). I/O controller sets IRQ line status high. CPU detects IRQ at beginning of fetch/execute. CPU saves state of running program and switches to an IRQ handler routine. Routine services the request. Control is returned to the previously running code

41
Q

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Problems with interrupt driven I/O

A

CPU still involved with each interrupt – Only transfers a single byte/word

42
Q

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did you know Only transfers a single byte/word

A

Disk or network transfers may be hundreds or thousands of bytes. IRQ handler code may be hundreds of instructions. Still too much overhead.

43
Q

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DMA

A

– Direct Memory Access (DMA) – Add a specialized kind of CPU that can directly transfer data from device to memory.

44
Q

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Purely programmed I/O requires special I/O instructions,

A

, I/O data and address registers, and polling loops that waste CPU resources.

45
Q

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Interrupt-driven I/O avoids

A

busy-waiting but is unsuitable for large block transfers due to interrupt handler execution overhead.

46
Q

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DMA combines PIO and IRQ handlers

A

with a special controller to transfer large amounts of block data efficiently directly to memory.

IT110 (10 decks)

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