export_week 10 chapter 8 cpu and memory design enhancement and implementation

Question 1

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▪ Current CPU Architecture Designs:

Answer 1

▪ Traditional modern architectures

▪ VLIW (Transmeta) – Very Long Instruction Word

▪ EPIC (Intel) – Explicitly Parallel Instruction Computer

Question 2

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Current CPU Architectures:

Answer 2

* IBM Mainframe series * Intel x86 family * IBM POWER/PowerPC family * Sun SPARC family

Question 3

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Problems with early CPU Architectures and solutions:

Answer 3

▪ Large number of specialized instructions were rarely used but added hardware complexity and slowed down other instructions ▪ Slow data memory accesses could be reduced by increasing the number of general purpose registers ▪ Using general registers to hold addresses could reduce the number of addressing modes and simplify architecture design

▪ Fixed-length, fixed format instruction words would allow instructions to be fetched and decoded independently and in parallel

Question 4

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how VLIW Architecture?

Answer 4

▪ Transmeta Crusoe CPU ▪ 128-bit instruction bundle = molecule ▪ Four 32-bit atoms (atom = instruction) ▪ Parallel processing of 4 instructions ▪ 64 general purpose registers ▪ Code morphing layer ▪ Translates instructions written for other CPUs into molecules ▪ Instructions are not written directly for the Crusoe CPU

Question 5

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EPIC Architecture

Answer 5

▪ 128-bit instruction bundle ▪ 3 41-bit instructions ▪ 5 bits to identify type of instructions in bundle * 128 64-bit general purpose registers * 128 82-bit floating point registers * Intel X86 instruction set included * Programmers and compilers follow guidelines to ensure parallel execution of instructions

Question 6

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Fetch-Execute Cycle Timing Issues?

Answer 6

▪ Computer clock is used for timing purposes for each step of the instruction cycle ▪ GHz (gighertz) – billion steps per second ▪ Instructions can (and often) take more than one step ▪ Data word width can require multiple steps

Question 7

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CPU Features and Enhancements

Answer 7

Separate Fetch/Execute Units Pipelining Multiple, Parallel Execution Units Scalar Processing Superscalar Processing Branch Instruction Processing

Question 8

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what include fetch unit ?

Answer 8

▪ Instruction fetch unit ▪ Instruction decode unit Determine opcode Identify type of instruction and operands ▪ Several instructions are fetched in parallel and held in a buffer until decoded and executed ▪ IP – Instruction Pointer register holds instruction location of current being processed

Question 9

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what is including in the Execute Unit?

Answer 9

▪ Receives instructions from the decode unit ▪ Appropriate execution unit services the instruction

Question 10

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define Instruction Pipelining ?

Answer 10

▪ Assembly-line technique to allow overlapping between fetch-execute cycles of sequences of instructions

Question 11

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define Scalar processing ?

Answer 11

Average instruction execution is approximately equal to the clock speed of the CPU

Question 12

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Branch Problem Solutions

Answer 12

▪ Separate pipelines for both possibilities ▪ Probabilistic approach ▪ Requiring the following instruction to not be dependent on the branch ▪ Instruction Reordering (superscalar processing)

Question 13

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Multiple, Parallel Execution Units what is it ?

Answer 13

▪ Different instructions have different numbers of steps in their cycle ▪ Differences in each step ▪ Each execution unit is optimized for one general type of instruction ▪ Multiple execution units permit simultaneous execution of several instructions

Question 14

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talk about Superscalar Processing?

Answer 14

▪ Process more than one instruction per clock cycle

▪ Separate fetch and execute cycles as much as possible

▪ Buffers for fetch and decode phases

▪ Parallel execution units

Question 15

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talk about Superscalar Issues

Answer 15

▪ Out-of-order processing – dependencies (hazards)

▪ Data dependencies

▪ Branch (flow) dependencies and speculative execution

▪ Parallel speculative execution or branch prediction

▪ Branch History Table

▪ Register access conflicts

▪ Rename or logical registers

Question 16

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why need Memory Enhancementsand what are they ?

Answer 16

Memory is slow compared to CPU processing speeds!
▪ 2Ghz CPU = 1 cycle in ½ of a billionth of a second
▪ 70ns DRAM = 1 access in 70 millionth of a second
▪ Methods to improvement memory accesses:
▪ Wide Path Memory Access
• Retrieve multiple bytes instead of 1 byte at a time
▪ Memory Interleaving
• Partition memory into subsections, each with its own address register and data register
▪ Cache Memory

Question 17

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Cache Memory

Answer 17

▪ Blocks: 8 or 16 bytes ▪ Tags: pointer to location in main memory ▪ Cache controller ▪ hardware that checks tags ▪ Cache Line ▪ Unit of transfer between storage and cache memory ▪ Hit Ratio: ratio of hits out of total requests ▪ Synchronizing cache and memory ▪ Write through ▪ Write back

Question 18

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Step-by-Step Use of Cache1

Answer 18

Question 19

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Performance Advantages of cache memory?

Answer 19

▪ Hit ratios of 90% common ▪ 50%+ improved execution speed ▪ Locality of reference is why caching works ▪ Most memory references confined to small region of memory at any given time ▪ Well-written program in small loop, procedure or function ▪ Data likely in array ▪ Variables stored togeth

Question 20

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Why do the sizes of the caches have to be different?

Question 21

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reasons for Multiprocessing?

Answer 21

▪ Reasons ▪ Increase the processing power of a system ▪ Parallel processing

Question 22

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Multiprocessor system in Multiprocessing is ?

Answer 22

▪ Tightly coupled ▪ Multicore processors - when CPUs are on a single integrated circuit

Question 23

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what is Multiprocessor Systems for ?

Answer 23

▪ Identical access to programs, data, shared memory, I/O, etc. ▪ Easily extends multi-tasking, and redundant program executio

Question 24

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▪ Two ways to configure Multiprocessor Systems

Answer 24

▪ Two ways to configure ▪ Master-slave multiprocessing ▪ Symmetrical multiprocessing (SMP)

Question 25

# ; tab , Master-Slave Multiprocessing, Master CPU?

Answer 25

▪ Manages the system ▪ Controls all resources and scheduling ▪ Assigns tasks to slave CPUs

Question 26

# ; tab , aAdvantages of Master-Slave Multiprocessing?

Answer 26

Advantages ▪ Simplicity ▪ Protection of system and data

Question 27

# ; tab , ▪ Disadvantages of Master-Slave Multiprocessing?

Answer 27

▪ Disadvantages ▪ Master CPU becomes a bottleneck ▪ Reliability issues – if master CPU fails entire system fails

Question 28

# ; tab , Symmetrical Multiprocessing

Answer 28

▪ Each CPU has equal access to resources ▪ Each CPU determines what to run using a standard algorithm

Question 29

# ; tab , ▪ Disadvantages of Symmetrical Multiprocessing

Answer 29

▪ Resource conflicts – memory, i/o, etc. ▪ Complex implementation

Question 30

# ; tab , Advantages Symmetrical Multiprocessing ?

Answer 30

▪ High reliability ▪ Fault tolerant support is straightforward ▪ Balanced workload

Question 31

# ; tab , General Enhancements – Use RISC-based techniques

Answer 31

– Fewer instruction formats, fixed-length → faster decoding – More general purpose registers → fewer memory accesses

Question 32

# ; tab , Clock cycle and instruction cycle

Answer 32

– Most instructions take several clock cycles to execute: Fetch the new instruction [IF]. Decode the instruction [ID]. Execute the instruction [EX]. Access memory (if needed) [MEM]. Write back to the registers [WB]

Question 33

# ; tab , Each stage takes a clock cycle, so complete execution takes 5 cycles. Can we do better?

Answer 33

Waiting for all five stages of instruction execution to complete is like building something from start to finish

Question 34

# ; tab , Clock cycle and instruction cycle Or can the CPU overlap the execution of several instructions at once because they’re all similar?

Answer 34

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Question 35

# ; tab , – Five stages of instruction execution

Answer 35


Question 36

# ; tab , Five stages of instruction execution

Answer 36


Question 37

# ; tab , Clock cycle and instruction cycle

Answer 37


Question 38

# ; tab , – Problems with pipelining

Answer 38

Dependencies (register interlock)—if an instruction needs a result from the immediately preceding instruction, that result won’t be written back until WB, but the result is needed in EX.

Question 39

# ; tab , Problems with pipelining

Answer 39

– Branching—when the instruction being executed is a branch, we can’t know if the branch will be taken until after stage 3. But by that time, other instructions are “in flight.”

Question 40

# ; tab , Clock cycle and instruction cycle

Answer 40


Question 41

# ; tab , Superscalar Processing

Answer 41

RISC and pipelining lets each functional unit in a CPU be fully utilized all of the time. – But, what if there were multiple ALUs or multiple decoders? Then multiple instructions could be executed at once. – Prerequisite: Multiple instructions should be fetched at once via a large path to memory.

Question 42

# ; tab , Superscalar Processing D

Answer 42


Question 43

# ; tab , Superscalar Processing DD

Answer 43


Question 44

# ; tab , – Problems with superscalar processing

Answer 44

– Same general categories as with pipelining: dependencies and branches – Except now forwards, stalls, or canceling may need to be between several functional units! – CPUs become very complex again, yet it is common to have 2 to 4 separate pipelines per core in modern processors.

Question 45

# ; tab , Did you know 1

Answer 45

RISC-based CPUs offer general performance enhancements due to simplified formats and single-clock cycle execution.

Question 46

# ; tab , Pipelining allows.....

Answer 46

multiple instructions to be in various stages of execution at once.

Question 47

# ; tab , Superscalar processing duplicates......

Answer 47

pipelines in a single core to have multiple instructions executing simultaneously.

Question 48

# ; tab , Data dependencies and branches are......?

Answer 48

hazards to both pipelining and superscalar architectures.

Question 49

# ; tab , Recall CPU Pipelining

Answer 49


Question 50

# ; tab , Three complementary approaches memory ?

Answer 50

All three are used simultaneously in the system design

Question 51

# ; tab , Wide path memory access

Answer 51


Question 52

# ; tab , Wide path memory access 1

Answer 52


Question 53

# ; tab , Wide path memory access 2

Answer 53


Question 54

# ; tab , Wide path memory access

Answer 54

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Question 55

# ; tab , Memory interleaving

Answer 55

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Question 56

# ; tab , Memory interleaving D

Answer 56

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Question 57

# ; tab , Cache Memory

Answer 57

Use a small amount of expensive SRAM as a buffer against the large amount of DRAM

Question 58

# ; tab , Cache Memory

Answer 58

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Question 59

# ; tab , Cache Memory

Answer 59

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Question 60

# ; tab , cache entries consists of ?

Answer 60

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Question 61

# ; tab , cache replacement algorithm ?

Answer 61

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Question 62

# ; tab , cache memory what should happen on memory write ?

Answer 62

Cache coherency gets particularly tricky with multiple cores and multiple levels of cache.

Question 63

# ; tab , DID you know

Answer 63

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