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IT110 > export_week 7 chapter 7 the cpu and memory > Flashcards

export_week 7 chapter 7 the cpu and memory Flashcards

1
Q

,

CPU: Major Components

A

▪ ALU

CU

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2
Q

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ALU

A

arithmetic logic unit)

▪ Performs calculations and comparisons

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3
Q

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CU

A

(control unit)

▪ Performs fetch/execute cycle

Accesses program instructions and issues commands to the ALU

Moves data to and from CPU registers and other

hardware components

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4
Q

,

Subcomponents: of the CPU

A

Memory management unit: supervises fetching

instructions and data from memory

I/O Interface: sometimes combined with memory

management unit as Bus Interface Unit

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5
Q

,

System Block Diagram

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imaget5ujrx-14A623EF3484D1AD610.png

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6
Q

,

Concept of Registers

A

▪ Small, permanent storage locations within the

CPU used for a particular purpose

▪ Manipulated directly by the Control Unit

▪ Wired for specific function

▪ Size in bits or bytes (not in MB like memory

▪ Can hold data, an address or an instruction

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7
Q

,

▪ How many registers does the LMC have?

▪ What are the registers in the LMC?

A

two the baskets

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8
Q

,

Use of Registers

A

▪ Scratchpad for currently executing program

•

Holds data needed quickly or frequently

▪ Stores information about status of CPU and currently

executing program

  • Address of next program instruction
  • Signals from external devices
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9
Q

,

what about General Purpose Registers

A

User-visible registers

Hold intermediate results or data values, e.g., loop counters

Equivalent to LMC’s calculator

Typically several dozen in current CPUs

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10
Q

,

Special-Purpose Registers (PC )

A

Program Count Register (PC)

▪ Also called instruction pointer

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11
Q

,

Special-Purpose Registers (IR)

A

Instruction Register (IR)

▪ Stores instruction fetched from memory

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12
Q

,

Special-Purpose Registers

A

▪ Memory Address Register (MAR)

▪ Memory Data Register (MDR)

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13
Q

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Status Registers

A

▪ Status of CPU and currently executing program

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14
Q

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▪ Flags

A

(one bit Boolean variable) to track condition like arithmetic carry and overflow, power failure, internal computer error

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15
Q

,

Register Operations

A

Stores values from other locations

(registers and memory)

▪ Addition and subtraction

▪ Shift or rotate data

▪ Test contents for conditions such as

zero or positive

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16
Q

,

Operation of Memory

A

▪ Each memory location has a unique address

▪ Address from an instruction is copied to the

MAR which finds the location in memory

▪ CPU determines if it is a store or retrieval

▪ Transfer takes place between the MDR and

memory

▪ MDR is a two way register

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17
Q

,

Relationship between MAR,

MDR and Memory

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageyl64qx-14A6244FA592BD3F909.png

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18
Q

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MAR-MDR Example

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagets74qx-14A6245FB8B15F5F3DA.png

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19
Q

,

Visual Analogy of Memory

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagewq1jrx-14A62465FD82D7612E8.png

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20
Q

,

Individual Memory Cell

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image5lihrx-14A6246EE3776B84806.png

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21
Q

,

memory capacity determined by two factors ?

A
  1. Number of bits in the MAR

LMC = 100 (00 to 99)

2 K where K = width of the register in bits

  1. Size of the address portion of the instruction

4 bits allows 16 locations

8 bits allows 256 locations

32 bits allows 4,294,967,296 or 4 GB

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22
Q

,

RAM:

A

Random Access Memory

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23
Q

,

what is RAM (Dynamic RAM)?

A

▪ Most common, cheap, less electrical power, less

heat, smaller space

▪ Volatile: must be refreshed (recharged with power)

  • 1000’s of times each second
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24
Q

,

SRAM (static RAM)

A

▪ Faster and more expensive than DRAM

▪ Volatile

▪ Small amounts are often used in cache memory

for high-speed memory access

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25
Q

,

Nonvolatile Memory?1

A

ROM

▪ Read-only Memory

▪ Holds software that is not expected to change over

the life of the system

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26
Q

,

Nonvolatile Memory?2

A

▪ EEPROM

▪ Electrically Erasable Programmable ROM

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27
Q

,

Nonvolatile Memory ?

A

Flash Memory

  • Faster than disks but more expensive
  • Uses hot carrier injection to store bits of data
  • Slow rewrite time compared to RAM
  • Useful for nonvolatile portable computer storage
28
Q

,

why two cycle process ?

A

▪ Two-cycle process because both

instructions and data are in memory

▪ Fetch

▪ Decode or find instruction, load from

memory into register and signal ALU

▪ Execute

▪ Performs operation that instruction requires

▪ Move/transform data

29
Q

,

LMC vs. CPU

Fetch and Execute Cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagesk5zqx-14A624C2B34604CD684.png

30
Q

,

Load Fetch/Execute Cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_253-14A624D51252008153D.png

31
Q

,

Store Fetch/Execute Cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_254-14A624DD0947E3E69CB.png

32
Q

,

ADD Fetch/Execute Cycle

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_255-14A624E59B9327AE000.png

33
Q

,

LMC Fetch/Execute

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_256-14A624ED42D413B7F75.png

34
Q

,

what is a bus?

A

▪ The physical connection that makes it possible

to transfer data from one location in the computer system to another

▪ Group of electrical or optical conductors for

carrying signals from one location to another

▪ Wires or conductors printed on a circuit board

▪ Line: each conductor in the bus

35
Q

,

▪ 4 kinds of signals buses ?

A
  1. Data
  2. Addressing
  3. Control signals
  4. Power (sometime
36
Q

,

Bus Characteristics

A

Number of separate conductors

Data width in bits carried simultaneously

Addressing capacity

Lines on the bus are for a single type of signal or

shared

Throughput - data transfer rate in bits per second

Distance between two endpoints

37
Q

,

Bus Characteristics

A

Number and type of attachments supported

Type of control required

Defined purpose

Features and capabilities

38
Q

,

Bus Categorizations

A

▪ Parallel vs. serial buses

▪ Direction of transmission

▪ Simplex – unidirectional

▪ Half duplex – bidirectional, one direction at a time

▪ Full duplex – bidirectional simultaneously

▪ Method of interconnection

39
Q

,

▪ Method of interconnection

A

▪ Point-to-point – single source to single destination

• Cables – point-to-point buses that connect to an external device

▪ Multipoint bus – also broadcast bus or multidrop bus

• Connect multiple points to one another

40
Q

,

Parallel vs. Serial Buses

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_257-14A6252FD871C12C7EA.png

41
Q

,

Point-to-point vs. Multipoint?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_258-14A6253D3BE69D10F44.png

42
Q

,

Classification of Instructions

A

▪ Data Movement (load, store)

▪ Most common, greatest flexibility

▪ Involve memory and registers

▪ What’s this size of a word ? 16? 32? 64 bits?

▪ Arithmetic

▪ Operators + - / * ^

▪ Integers and floating point

43
Q

,

Classification of Instructions2

A

▪ Boolean Logic

▪ Often includes at least AND, XOR, and NOT

▪ Single operand manipulation instructions

▪ Negating, decrementing, incrementing, set to 0

44
Q

,

More Instruction Classifications

A

Bit manipulation instructions

▪ Flags to test for conditions

Shift and rotate

Program control

Stack instructions

Multiple data instructions

I/O and machine control

45
Q

,

Register Shifts and Rotates

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageq7mcrx-14A6255ACE7362A80AA.png

46
Q

,

Program Control Instructions

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_259-14A6256C6882B957372.png

47
Q

,

Stack Instructions

A

▪ Stack instructions

▪ LIFO method for organizing information

▪ Items removed in the reverse order from that in which they

are added

48
Q

,

Fixed Location Subroutine

Return Address Storage: Oops!

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagejao1qx-14A6257C19A43059998.png

49
Q

,

Stack Subroutine Return Address Storage

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagejcs1qx-14A62582D275BF9888A.png

50
Q

,

Stack Subroutine Return Address Storage

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imagejcs1qx-14A625918221CE1FD03.png

51
Q

,

Block of Memory as a Stack

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/imageko3brx-14A6259D73E4211963E.png

52
Q

,

Multiple Data Instructions

A

▪ Perform a single operation on multiple pieces of data simultaneously

▪ SIMD: Single Instruction, Multiple Data

▪ Commonly used in multimedia, vector and array processing applications

53
Q

,

Instruction Elements

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_260-14A625B3A3D2AB36CA7.png

54
Q

,

Instruction Format

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_261-14A625B1AE748A4B5BD.png

55
Q

,

▪ Instruction is ?

A

▪ Direction given to a computer

▪ Causes electrical or optical signals to be sent through

specific circuits for processing

56
Q

,

Instruction set ?

A

▪ Design defines functions performed by the processor

▪ Differentiates computer architecture by the

Number of instructions

Complexity of operations performed by individual instructions

Data types supported

Format (layout, fixed vs. variable length)

Use of registers

Addressing (size, mode

57
Q

,

Instruction Word Size

A

▪ Fixed vs. variable size

▪ Pipelining has mostly eliminated variable

instruction size architectures

▪ Most current architectures use 32-bit or 64-bit words

▪ Addressing Modes

▪ Direct

Mode used by the LMC

▪ Register Deferred

▪ Also immediate, indirect, indexed

58
Q

,

Instruction Format Examples

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/image0ah4qx-14A625E16832BEC9267.png

59
Q

,

What is a bus?

A

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_262-14A626011877D139C3A.png

60
Q

,

what is bus

A

A line is a single conductor carrying an electrical signal between components.

It carries one bit of information.

– A bus is a collection of lines used to transfer multiple bits of information at a

time.

– The width of a bus is the number of lines

61
Q

,

compare Point-to-point vs. multipoint ?

A

– Point-to-point busses connect two components

– Multipoint busses connect more than two component

62
Q

,

what is contention

A

Simplex busses transmit only in one direction.

Half-duplex busses transmit in both directions but not simultaneously.

Full-duplex busses transmit in both directions at the same time.

If busses are not full duplex, then a protocol must control access to prevent

collisions on the bus

– CSMA/CD on Thinnet Ethernet (IEEE 802.3)

– CSMA/CA on WiFi (IEEE 802.11)

63
Q

,

Busses carry what do they do ?

A

data from one component to another.

64
Q

,

The width of the bus determines

A

the number of bits at a time that can be

transmitted.

65
Q

,

When the bus is half duplex or is multipoint, then an

A

an algorithm is needed to

control access to the bus to prevent collisions.

IT110 (10 decks)

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