Overview of Systems on Chip (SoCs)

Question 1

What is a SoC?

Answer 1

System on Chip
An integrated circuit possibly containing:
1. Processors (CPU, GPU etc.)
2. Memory (ROM, RAM etc.)
3. Interconnects (bus)
4. External interfaces (USB, Ethernet)

Question 2

Why use a SoC?

Answer 2

1. Tight coupling between components
2. Can be customised
3. Can be built from different parts

Question 3

A SoC likely has heterogenous cores. What does this mean?

Answer 3

1 big core and 1 little core
Big cores do heavy lifting, little cores do background tasks

Question 4

A SoC likely has a DRAM interface. What is this?

Answer 4

Components to talk to low power DDR off-chip memory

Question 5

What is Flynn’s Taxonomy? What are the 4 classes?

Answer 5

Classification of computing systems showing parallelism in instruction and data streams
1. SISD
Simple processor
2. MISD
Run multiple instructions on the same data, verify cores are making correct decisions eg. safety critical systems
3. SIMD
Vector processing, energy efficient
4. MIMD
Multicore, like standard general purpose CPUs

Question 6

Draw a diagram to show the 4 classes of Flynn’s Taxonomy

Answer 6

.

Question 7

We can always add more cores but performance is limited by ?

Answer 7

parallelism
This is because speedup from adding more cores depends on how much we split up and parallelise the task

Question 8

What does Amdahl’s Law show? Give the equation

Answer 8

Shows expected performance as cores increase
speedup(n) = 1/(B + ((1 - B)/N))
n = number of cores
B = sequential fraction

Question 9

What 2 things does Amdahl’s Law imply?

Answer 9

1. We need to write very parallel programs to make best use of the cores. Speedup is limited by the sequential part so minimise this
2. Maximum system improvement is limited by fraction being improved

Question 10

Give the equation for Gustafson’s Law

Answer 10

speedup(n) = n + (1-n)B
n = number of cores
B = sequential fraction

Question 11

What does Amdahl’s Law assume?

Answer 11

Fixed problem size - what ifs the speedup if I parallelise this?

Question 12

What does Gustafson’s Law assume?

Answer 12

Fixed execution time - can do more work in same time because more parallelism

Question 13

What does Gustafson’s Law imply?

Answer 13

When given more computing power, programmers increase the problem size

Question 14

Draw a graph to show Amdahl’s Law

Answer 14

.

Question 15

Draw a graph to show Gustafson’s Law

Answer 15

.

Question 16

In what device may on-chip ROM and RAM be sufficient?

Answer 16

Microcontroller

Question 17

In what device may memory need to be placed off-chip too?

Answer 17

SoC for a mobile phone/tablet

Question 18

Give 2 reasons to place all memory on chip

Answer 18

1. Tighter integration good for latency and bandwidth
2. Less need for a cache

Question 19

Give 2 reasons to leave memory on a separate chip

Answer 19

1. May not be enough space on-chip
2. Off-chip memory is more generic so has greater applicability

Question 20

What is chip stacking?

Answer 20

How we arrange memory chips on top of SoC

Question 21

List the two methods of chip stacking

Answer 21

1. Package on package
2. 3D die stacking

Question 22

What is package on package chip stacking?

Answer 22

Memory chip is put directly on top of SoC and ball grid array connects the two

Question 23

What is 3D die chip stacking?

Answer 23

Silicon wafers are directly placed together with through-silicon vias connecting the dies

Question 24

Draw a diagram of a DRAM cell

Answer 24

.

Question 25

What is a DRAM cell composed of?

Answer 25

1 transistor 1 capacitor - holds the charge but leaks so needs refreshing Wordline - selects the bit Bitline - contains data read out and data written in

Question 26

How much data can be stored in a DRAM cell?

Answer 26

1 bit

Question 27

Draw a diagram of a DRAM bank

Answer 27

.D

Question 28

Draw a diagram of a DRAM device

Answer 28

.

Question 29

How are cells organised in a DRAM bank?

Answer 29

Organised into arrays Rows = wordlines Columns = bitlines

Question 30

What is a DRAM bank?

Answer 30

DRAM cells are organised into arrays. A DRAM bank is a group of arrays

Question 31

How much data does an array provide?

Answer 31

A single bit, so multiple arrays are needed to access more than one bit at a time

Question 32

What is a DRAM device?

Answer 32

Contain several banks

Question 33

How do banks in a DRAM device operate?

Answer 33

Operate independently. Each contains N arrays and provides N bits of data

Question 34

What is a DRAM rank?

Answer 34

DRAM devices can be arranged in ranks All devices in a rank operate together, but ranks are independent

Question 35

What gives bandwidth?

Answer 35

Concurrency at ranks and banks

Question 36

What allows parallel access?

Answer 36

Synchronised operation at devices and arrays

Question 37

Look over 64-bit read example

Answer 37

.

Question 38

What are the 5 DRAM commands and which low-level actions do they define?

Answer 38

1. Row access - move data to sense amps, then back 2. Column read - move data from sense amps to bus 3. Column write - move data from bus to sense amps 4. Precharge - reset sense amps and bitlines 5. Refresh - read out data then restore

Question 39

What do the sense amps do?

Answer 39

Act like buffers, store most recent row that was accessed, to access another row they must be reset

Question 40

How does multiple array access in a bank work?

Answer 40

Would access the same cell position in all N arrays to get N-bit value

Question 41

What does the memory controller do?

Answer 41

Handles DRAM accesses, responsible for converting processor requests into DRAM commands (select bank, row, column, precharge if close-page)

Question 42

What is an open-page policy?

Answer 42

Does not reset sense amps after memory access Sense amps can store whole row of data, like a cache line

Question 43

What are the advantages and disadvantages of an open-page policy?

Answer 43

+ Reduced latency when reading from that row again + Great for sequential access to different columns - Requires explicit rest when accessing another row

Question 44

What is a close-page policy?

Answer 44

Resets and precharges sense amps after memory access

Question 45

What is an advantage of a close-page policy?

Answer 45

+ Works well with access patterns with little locality

Question 46

What does the memory controller have to do with timings?

Answer 46

Issues each command so in sequence to minimise time each command takes, must respect key DRAM timings