Multicore Processors (2) Flashcards
What is memory consistency?
What ordering do we see between reads and writes from another core that uses the same shared memory
Look at consistency example
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Look at reordering memory ops example
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Why might loads and stores to different addresses get reordered?
To allow higher performance from core
What can reordering memory ops lead to?
Non-intuitive situations
What does coherence ensure?
That cached data written by a core is seen by others
What does the memory consistency model determine?
The order that operations from one core can be seen by others
What is relaxed consistency? When do we want to use this?
Some loads and stores can bypass each other
Relative ordering between operations to the same address is maintained
Want relaxed consistency processors
What type of consistency do we want for shared data?
Sequential (strong) consistency
All reads and writes by a single processor are seen in the order they occur
Describe a memory barrier
Guarantee ordering of memory operations within a core - used to force sequential consistency
All prior memory operations complete before the barrier finishes execution ie. store after a barrier can’t overtake a load before it
Look at example of memory barrier
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What are atomic operations?
Uninterruptible sequences of operations that appear to all occur as one
Used to create software synchronisation primitives eg. locks, thread barriers etc.
Describe Read-Modify-Write (RMW)
Most basic class of atomic operation
Provide ability to read a memory location and simultaneously write a new value back
Give 2 examples of RMW
- Atomic exchange
- Fetch and add
Draw a diagram of atomic exchange (between X in cache and R1 in core)
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What is atomic exchange? Why is it difficult in RISC machines?
Read and write in one interruptible instruction
But would require a complex instruction and in RISC we prefer simple load or store instructions
What can we use instead of atomic exchange?
Load reserved / store conditional - instead of one instruction, provide two halves
Describe load reserved / store conditional
Instructions are linked together: store only succeeds if X hasn’t changed, any write to X causes the store to fail
Source register contains 1 on success, 0 on failure
Write the RISC instruction for atomic exchange between X in cache and R1 in core
atomic_exch X, r1
Write the RISC instructions for load reserved / store conditional between X in cache and R1 in core
load_reserved r0, X
store_conditional r1, X
Write out the instruction sequence for atomic exchange
xchg: mov r3, a0
lr r4, 0(r1)
sc r3, 0(r1)
beqz r3, xchg (fail and branch back to top of loop)
mov a0, r4
Write out the instruction sequence for fetch-and-add
fadd: lr r4, 0(r1)
add r4, r4, 1
sc r4, 0(r1)
beqz r4, fadd
Write out the instruction sequence for a more optimised spin lock
lock: lr r4, 0(r1)
bneq r4, lock
mov r3, #1
sc r3, 0(r1)
beqz r3, lock
Write out the instruction sequence for a simple spin lock
lock: mov r3, #1 (take lock)
lr r4, 0(r1)
sc r3, 0(r1)
beqz r3, lock (check if store conditional was successful)
bneq r4, lock (if lock in r4 contains 1 staret again because lock has been taken)
