OS Support Flashcards
What is the main purpose of virtual memory?
To give each application the illusion that it has its own address space, isolating processes
What is responsible for translating virtual to physical addresses?
Processor and OS
What are the advantages and disadvantages of using megapages instead of pages?
+ Optimise page table
+ Exploit locality
- Less flexibility to move data around
When paging, we can migrate rarely used pages to disk. What are the advantages and disadvantages of this?
+ Gives the illusion of a bigger memory
+ Useful to deal with programs with a larger working set
- Slow if paging to magnetic disk
- Risks wearing out flash disk
Draw a diagram demonstrating the concept of address translation
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What is the trade-off when increasing cache size?
+ Decrease capacity misses
- May increase access time
What is the trade-off when increasing associativity?
+ Decrease conflict misses
- May increase access time
What is the trade-off when increasing cache-line size?
+ Decrease compulsory misses
- Increases miss penalty
- Very large cache line size may increase miss rate due to pollution
What is a level-1 cache?
Attached to CPU, small, low latency
What is a level-2 cache?
Services misses from leve1/primary cache, larger, slower but still faster than main memory, off-chip
What services level-2 cache misses?
Main memory, of level-3 cache if the system has one
Which cache is the last-level cache?
Closest to DRAM
Look over multilevel cache example calculation slide
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What is a TLB?
Translation Look-aside Buffer
Cache of PTEs (ie. cache of page table)
Why do we use a TLB?
Address translation without it would always require 2 memory references per instruction: one to access the PTE to get the physical address the virtual address maps to, then the actual memory access using the physical address
The TLB is a fast cache of PTEs within the CPU so frequently accessed pages only require 1 memory access
What property enables TLBs to help performance?
Access to page tables has good locality ie. if you access one bit in a page you are likely to access another bit in the same page
TLB lookup is usually performed ? ? ? L1 cache access
in parallel to
Describe the structure of a page table
If a page is present in memory:
Contains status bits: valid, dirty, reference. Table of physical addresses, indexed by virtual address
If page is not present in memory:
PTE refers to a location in swap space on disk
Software Page Fault Handler invoked
Describe the structure of the TLB
Contains status bits: valid, dirty, reference. Table of tag and physical addresses, indexed by virtual addresses
Draw a diagram demonstrating how the TLB is used in virtual address translation
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How is a TLB miss handled if the page is in memory?
Load the PTE from memory and retry
Could be handled in hardware or in software
How is a TLB miss handled if the page is not in memory (page fault)?
OS handles fetching page and updating page table, then restarts faulting instruction
What is a hardware page table walker?
Piece of software that is invoked if there is a TLB miss
Walks the page table to search for the PTE
If PTE is found it gets put into TLB, if PTE not found there is an exception to OS.
Memory operations are then typically replayed
What is a page table register?
Register in CPU that points to page table in physical memory
