More Processor Pipelines Flashcards
We use ? to control the flow of data in our pipeline
D flip-flops
Draw a diagram if a D flip-flop
.
What is a pipeline latch?
Bank of D flip-flops, one for each bit of data
Draw the processor pipeline, adding pipeline latches
.
The mux in the processor pipeline would have more inputs if we are using ?
forwarding
What pipelining issue do we get from write-back to load?
When we write loaded data back to the register file we can write it back to the wrong rd. This can be overcome by propagating control information along the data-path
What is a branch target buffer?
Cache of target addresses so that branch doesn’t need to reach ID or EX to do prediction
Indexed by PC of when instructions were fetched
If hit and instruction is branch predicted taken can fetch target immediately
What is a branch prediction buffer?
Indexed by recent branch instruction addresses
Stores outcome (taken/not taken)
How is a branch prediction buffer used in dynamic branch prediction?
Check table, expect same outcome
Start fetching
If wrong, flush pipeline
What is the relationship between the branch prediction buffer and branch target buffer?
Branch prediction buffer forwards PC of branch to branch target buffer
How can we describe exceptions and interruptions?
Unexpected events requiring a change in flow of control
What is the difference between exceptions and interrupts?
Exceptions arise within the CPU (eg. undefined opcode) but interrupts come from an external I/O controller
How are exceptions handled?
- Save PC of interrupting instruction
- Save indication of the problem
- Flush the instructions and any instructions earlier in the pipeline
Then if precise exception: handler executes then returns to instruction which is refetched and reexecuted
If imprecise exception: cannot recover from exception
What is pipelining?
Executing multiple instructions in parallel
How can we increase instruction level parallelism (ILP)?
- Deeper pipeline
- Multiple issue
Give an advantage and disadvantage of a deeper pipeline
Advantage: less work per stage so shorter clock cycle
Disadvantage: more forwarding paths and risk of bubbles due to hazards
What is multiple issue?
Replicate pipeline stages to create multiple pipelines, so can start multiple instructions per clock cycle
What type of hazards do branches cause?
Control flow
How can we get rid of data hazards?
Use more than one data forwarding path
How could we stop erroneously fetched instructions from completing?
- Flush the instructions from the pipeline
- Add an epoch number (colour) to fetched instructions and change the colour on a branch so the wrong colour instructions are ignored
What is load hoisting?
It is a general compiler optimisation that aimsto issue load instructions as early as possible
Available parallelism is limited by ?
dependencies
Complexity leads to the ? ?
power wall
