Digital Systems Design Flashcards
Logic level is ?
discrete
What is used to store state and control the flow of information in clocked circuits?
D flip-flops
What is setup time?
Time D input is stable before the clock edge (usually positive)
What is hold time?
Time D input is stable after the clock edge (usually negative)
Why is hold time necessary?
To tolerate clock jitter
Draw a D flip-flop
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What is a clock tree?
An H-tree physical structure that aims to propagate clock to every part of the chip so that the clock edge appears at the same time everywhere (ie. low clock skew)
Draw an example of a clock tree
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Draw the state transition graph for a 2-bit counter
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Draw the state transition table for a 2-bit counter
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ADD OTHER DIG EL STUFF NEEDED
Use Boolean minimisation using K-maps to find expressions for both next state bits
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Revise D flip flops
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Revise state transition graphs, state transition tables, boolean minimisation using K-maps and circuit sketching (including circuits that contain D flip flips)
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Draw the circuit diagram for a 2-bit counter
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Revise System Verilog (see summary sheets)
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Draw a diagram showing the process of going from a description of a circuit in a Hardware Description Language (HDL) to an implementation of this circuit
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What happens in the synthesis stage?
SystemVerilog files are compiled (synthesised) into a lower-level description. This is typically a gate-level netlist (directed graph) of components linked by wires. Optimisations are performed
Give 3 optimisations that happen during synthesis
- Boolean optimisation
- Optimal state assignment
- Retiming for timing closure (can move combinational logic before or after flip flips for optimisation)
What happens in the place and route stage?
Physical components are placed onto physical locations on a chip or FPGA. Wires are routed between these components to complete a physical netlist. The process stops once constraints are met
Process of turning a diagram of a netlist into a physical netlist
Which 3 constraints are applied in place and route?
- Area constraints
- Location constraints
- Timing (performance) constraints
Can place and route be automated?
Yes. Automated approaches are highly effective but are time consuming for large designs with constraints that are difficult to meet
What happens in the timing analysis stage?
Given the physical netlist and a detailed physical model, determine the longest combinatorial paths in a circuit. This is used to determine whether the maximum clock frequency is safe (not what it could be). It ensures the digital time abstraction is still valid including setup and hold times on D flip flops and managing clock skew
How can you work out the maximum clock frequency?
Change the constraints and repeat place and route to see if the circuit could go faster
