๐๐ต๐ฎ๐ฝ๐๐ฒ๐ฟ ๐ญ๐ฌ: Memory Interface Flashcards
What are the four common types of memory
ROM, EEPROM, SRAM, DRAM
The least significant address input
A0
are the points at which data are entered for storage or extracted for reading.
Data Connections
An 8-bit-wide memory device is often called a ________ memory
byte-wide
o Select a memory location within the memory device
- Address inputs
o Have a set of data outputs or inputs/outputs
- Memory devices
o Selects or enables the memory device
- Chip select (CS)
o Also called Chip enable (CE)
- Chip select (CS)
o Also called Select (S)
- Chip select (CS)
o Gate
- Output enable (OE)
o Control input often found on a ROM
- Output enable (OE)
o must be active to perform a memory write
- Write enable (WE)
o permanently stores programs and data that are resident to the system and must not change when power supply is disconnected
- read-only memory (ROM)
o often called nonvolatile memory
- read-only memory (ROM)
o more commonly used when software must be changed often or when too few are in demand to make the ROM economical
- erasable programmable read-only memory (EPROM)
o programmed in the field by burning open tiny NI-chrome or silicon oxide fuses
- programmable read-only memory (PROM)
also called Flash memory
- electrically erasable programmable ROM (EEPROM)
also called EAROM (electrically alterable ROM)
- electrically erasable programmable ROM (EEPROM)
also called NOVRAM (nonvolatile RAM)
- electrically erasable programmable ROM (EEPROM)
o Newer type of read-mostly memory (RMM)
- electrically erasable programmable ROM (EEPROM)
o retain data for as long as DC power is applied
- Static RAM memory devices
o no special action (except power) is required to retain stored data
- static memory
- essentially the same as SRAM, except that it retains data for only 2 or 4 ms on an integrated capacitor
Dynamic RAM (DRAM) Memory
- Two special pins
o Column address strobe (CAS)
o Row address strobe (RAS)
o Latest DRAM
- DDR (double-data rate) memory device
- PLD
o Programmable logic device
- Three SPLD (simple PLD)
PLA
PAL
GAL
o PLA
๏ง Programmable logic array
o PAL
๏ง Programmable array logic
o GAL
๏ง Gated array logic
- CPLD
o Complex programmable logic devices
- FPGA
o Field programmable gate arrays
- FPIC
o Field programmable interconnect
- ASIC
o Application-specific integrated circuit
o internally structured as a programmable array of combinational logic circuits
- Combinatorial Programmable Logic Arrays
- HDL
o Hardware description language
- VDHL
o Verilog HDL
o often called to location FFFF0H
- Cold-start location
- SECDED
o Single error correction/double error correction
o the 16-bit data bus must be divided into two separate sections called the
- Banks
o holds all the even numbered memory locations
- low bank
o holds all the odd-numbered memory locations
- high bank
o Contain a 64-bit data bus which requires either eight decoders or eight separate write signals.
- Pentium through Core2 microprocessors
o requires address multiplexing and refreshing
- Dynamic RAM
o Extended data output
- EDO
o stores the 256 bits selected by RAS into latches
- EDO
o used with most newer systems in one form or another because of its speed
- SDRAM
- SDRAM
o Synchronous Dynamic RAM
o Double data rate memory
- DDR
o latest improvement in a long string of modifications to DRAM
DDR
