๐๐ต๐ฎ๐ฝ๐๐ฒ๐ฟ ๐ต: 8086/8088 Hardware Specifications Flashcards
Where are 8086 and 8088 microprocessors packaged in?
dual in-line packages (DIPs)
How many pins does dual in-line packages have?
40
contain the rightmost 8 bits of the memory address or I/O port number whenever ALE is active or data whenever ALE is inactive.
AD7-AD0; Address/Data Bus
provides the upper-half memory address bits that are present throughout a bus cycle
A15-A8; Address Bus
Compose the upper multiplexed
address/data bus on the 8086
AD15-AD8; address/data bus
Are multiplexed to provide address signals A19-A16 and also status bits S6-S3.
A19/S6-A16/S3; address/status bus
Whenever ____ is a logic 0, the data bus is receptive to data from the memory or I/O devices connected to the system.
Rฬ Dฬ ; read signal
is controlled to insert wait states into the timing of the microprocessor.
READY
used to request a hardware interrupt
INTR; Interrupt Request
Is an input that is tested by the WAIT instruction
Tฬ Eฬ Sฬ Tฬ
INTA
Interrupt Acknowledge
Is similar to INTR except that it does not check to see whether the IF flag bit is logic 1
Non-Maskable Interrupt (NMI)
causes the microprocessor to reset itself if this pin is held high for a minimum of four clocking periods
RESET
provides the basic timing signal to the microprocessor
Clock (CLK)
provides a +5.0 V, ยฑ10 % signal to the microprocessor
Voltage Common Collector (VCC)
is the return for the power supply
Ground (GND)
selects either minimum mode or maximum mode operation for the microprocessor
Minimum/Maximum (MN/Mฬ Xฬ )
used in the 8086 to enable the most-significant data bus bits (D15โD8) during a read or a write operation
Bus High Enable (Bฬ Hฬ Eฬ S7)
is obtained by connecting
the MN/Mฬ
Xฬ
pin directly to +5.0 V
Minimum Mode Pins
This pin indicates that the microprocessor address bus contains either a memory address or an I/O port address
IO/Mฬ or M/Iฬ Oฬ
is a strobe that indicates that the 8086/8088 is outputting data to a memory or I/O device
Write Line (Wฬ Rฬ )
is normally used to gate the interrupt vector number onto the data bus in response to an interrupt request
Iฬ Nฬ Tฬ Aฬ
shows that the 8086/8088 address/data bus contains address information
Address Latch Enable (ALE)
shows that the microprocessor data bus is transmitting or receiving data
Data Transmit/Receive (DT/Rฬ )
activates external data bus buffers
Data Bus Enable (DEN)
If the ____ signal is a logic 1, the microprocessor stops executing software and places its address, data, and control bus at the high-impedance state, if it is a logic 0, the microprocessor executes software normally.
HOLD
Indicates that the 8086/8088 has entered the hold state
Hold Acknowledge (HLDA)
This signal is combined with IO/Mฬ and DT/Rฬ to decode the function of the current bus cycle
Single Sign-on (Sฬ Sฬ 0ฬ )
is obtained by connecting the MN/Mฬ Xฬ pin to ground
Maximum Mode Pins
indicate the function of the current bus cycle
Status Bits (Sฬ 2ฬ , Sฬ 1ฬ , and Sฬ 0ฬ )
request direct memory accesses during maximum mode operation
Request/Grant
(Rฬ
Qฬ
/Gฬ
Tฬ
1ฬ
and Rฬ
Qฬ
/Gฬ
Tฬ
0ฬ
)
is used to lock peripherals off the system
Lฬ Oฬ Cฬ Kฬ
show the status of the internal instruction queue
Queue Status (QSโ and QSโ)
is an ancillary component to the 8086/8088 microprocessors
8284A Clock Generator
are provided to qualify the bus ready signals, RDY1 and RDY2, respectively
Address Enable (Aฬ Eฬ Nฬ 1ฬ and Aฬ Eฬ Nฬ 2ฬ )
are provided, in conjunction with the Aฬ Eฬ Nฬ 1ฬ and Aฬ Eฬ Nฬ 2ฬ pins, to cause wait states in an 8086/8088-based system
Bus Ready (RDY1 and RDY2)
selects either one or two stages
of synchronization for the RDY1 and RDY2 inputs
Ready Synchronization (Aฬ Sฬ Yฬ Nฬ Cฬ )
an output pin that connects to the 8086/8088 READY input
READY
connect to an external crystal used as the timing source for the clock generator and all its functions
Crystal Oscillator (X1 and X2)
chooses the clocking source for the
8284A
Frequency Crystal (F/Cฬ )
provides the CLK input signal to the 8086/8088 microprocessors and other components in the system
Clock Output (CLK)
is one sixth the crystal or EFI input frequency, and has a 50% duty cycle
Peripheral Clock (PCLK)
is a TTL-level signal that is at the same frequency as
the crystal or EFI input
Oscillator Output (OSC)
is often connected to an RC network that provides power-on resetting
Reset Input (Rฬ Eฬ Sฬ )
is connected to the 8086/8088 RESET input pin
Reset Output (RESET)
is used whenever the EFI input provides synchronization in systems with multiple processors
Clock Synchronization (CSYNC)
connects to the ground
GND
connects to +5.0 V with a tolerance of ยฑ10%
Power Supply (VCC)
If more than 10 unit loads are attached to any bus pin, the entire 8086 or 8088 system must be _____
buffered
provides the memory and I/O with the memory address or the I/O port number
Address Bus
transfers data between the microprocessor and the memory and I/O in the system
Data Bus
provides control signals to the memory and I/O
Control Bus
i an extra clocking period, inserted between T2 and T3 to lengthen the bus cycle
Wait State (Tw)
