Chapter 9 - (โ๐ฃ๐บ ๐๐ฆ๐ง๐งโ) Flashcards
__-pin dual in-line packages
40
- DIPs
o Dual in-line packages
- Which microprocessor uses M/IO
8086
- Which microprocessor uses IO/M
8088
Power Supply Requirements in Voltage and Tolerance
5V +-10% tolerance
o 8086 Max current supply
360 mA
o 8088 Max current supply
340 mA
Temperature of operation
- Between 32 and 180 F
Logic 0 V max (input char.)
๏ง 0.8 V max
Logic 1 V max (input char.)
๏ง 2.0 V max
Max current (input char.)
+- 10uA
Logic 0 V max (output char.)
๏ง 0.45 V max
Logic 0 I max (output char.)
๏ง 2.0 mA max
Logic 1 V max (output char.)
๏ง 2.4 V max
Logic 1 I max (output char.)
๏ง -400 uA max
Pin Connection (8086 & 8088)
o Address/data bus lines are multiplexed address data bus of 8088
- AD7 โ AD0
Pin Connection (8086 & 8088)
o Address Latch Enable
- ALE
Pin Connection (8086 & 8088)
o Address bus provides the upper-half memory address bits that are present throughout bus cycle
- A15-8
Pin Connection (8086 & 8088)
o Address/data bus lines compose the upper multiplexed address/data bus on the 8086
o A15-A8 when ALE is Logic 1
- AD15-AD8
Pin Connection (8086 & 8088)
o Address/status bus bits are multiplexed to provide address signals A19-A16, S6-S3
- A19/S6 โ A16/S3
RD
Read
Pin Connection (8086 & 8088)
o When read signal is L0, data bus is receptive to data from the memory or I/O devices connected
- RD
Pin Connection (8086 & 8088)
o Insert wait states into the timing of the microprocessor
- READY
o Request a hardware interrupt
- INTR
- INTR
o Interrupt request
o Input that is tested by the WAIT instruction
- TEST
- NMI
o Non-maskable interrupt
o Similar to INTR except it does not check to see whether the IF flag is L1
- NMI
o Causes the microprocessor to reset itself if this pun is held high for 4 clocking periods
- RESET
- CLK
o Clock
o Provides the basic timing signal
- CLK
o Power supply input provides a 5V, +- 10% signal
- VCC
o Return for the power supply
- GND
- MN/MX
o Minimum/maximum
o Selects either min mode or max mod operation for the microprocessor
- MN/MX
- BHE S7
o Bus high enable
o Enable the most significant data bus bits during a read or write operation
- BHE S7
o Selects memory or I/O
- IO/M (8088) or M/IO (8086)
o Indicates that the microprocessor address bus contains either a memory address or an I/O port address
- IO/M (8088) or M/IO (8086)
- WR
o Write line
o Strobe that indicates that the 8086/8088 is outputting a data to a memory or I/O device
- WR
- INTA
o Interrupt acknowledge
o Response to the INTR input pin
- INTA
- ALE
o Address latch enable
o Shows that address/data bus contains address information
- ALE
- DT/R
o Data transmit/receive
o Shows that the microp data bus is transmitting (DT/R = 1) or receiving (DT/R = 0) data
- DT/R
- DEN
o Data enable
o Activates external data bus buffers
- DEN
o Hold input
o Requests a direct memory access
- HOLD
- DMA
o Direct memory access
- HLDA
o Hold acknowledge
o Indicates that the 8086/8088 has entered the hold state
- HLDA
o Equivalent to the So pin in max mode operation of the microp
- SS0
o Status bits indicate the function of the current bus cycle
- S2, S1, and S0
- RQ/ GT1 and RQ/GT0
o Request/grant pins
o Request direct memory access during max mode operation
- RQ/ GT1 and RQ/GT0
o Used to lock peripherals off the system
- LOCK
- QS1 and QS0
o Queue status
o Show the status of the internal instruction queue
- QS1 and QS0
- Ancillary component to 8086/8088 microp
8284A Clock Generator
- AEN1 and AEN2
o Address enable pins
o Provided to qualify the bus ready signals
- AEN1 and AEN2
- RDY1 and RDY2
o Bus ready
o Provided, in conjunction with AEN1 and AEN2, to cause wait states
- RDY1 and RDY2
- X1 and X2
o Crystal oscillator
o Connect to an external crystal used as the timing source for the clock generator etc.
- X1 and X2
- F/C
o Frequency/crystal
o Chooses the clocking source for 8284A
- F/C
- CLK
o Clock output
o Provides the CLK input signal to the 8086/8088
- CLK
- PCLK
o Peripheral clock
o One sixth the crystal or EFI input frequency, has 50% duty cycle
- PCLK
- OSC
o Oscillator output
o TTL-level at same frequency as the crystal or EFI input
- OSC
- RES
o Reset input
o Active low input to 8284A
- RES
o Reset output is connected to the 8086/8088 RESET input pin
- RESET
- CSYNC
o Clock synchronization
o Used whenever the EFI input provides synchronization in systems with multiple processors
- CSYNC
o Connects to ground
- GND
o Connects to 5 V +-10% tolerance
- VCC
Three buses
o Address bus
o Data bus
o Control bus
- Bus cycles = ____ system-clocking periods
four
- 8086 __ data bus bits
16
- 8088 has __ data bus bits
8
- Sampled at end of T2
READY Input
- Synchronized ready input to the 8284A clock generator
RDY
o Least expensive way to operate the 8086/8088 microp
- Minimum mode operation
o Some control signals must be externally generated
- Maximum mode operation
o System operated in maximum mode must have this
o Provide the signals eliminated
- 8288 Bus Controller
o Connected to the status output pins on the 8086/8088 microp
- S2, S1, and S0
o Provides internal timing
- CLK
o Demultiplex address/data
- ALE
o Controls the bidirectional data bus buffers
- DEN
o Output by the 8288 to control the direction of the bidirectional data bus buffers
- DT/R
o Causes the 8288 to enable the memory control signals
- AEN
o Enables the command output pins on the 8288
- CEN
o I/O bus mode input selects either the I/O bus mode or system bus mode operation
- IOB
- AIOWC
o Advanced I/O write command
o Used to provide I/O with an advanced I/O write control signal
- AIOWC
o I/O read command output provides I/O with its read control signal
- IORC
o I/O write command output provides I/O with its write control signal
- IOWC
- AMWT
o Advanced memory write
o Provides memory with an early or advanced write signal
- AMWT
- MWTC
o Memory write control
o Provides memory with its normal write control signal
- MWTC
- MRDC
o Memory read control
o Provides memory with its normal read control signal
- MRDC
- INTA
o Interrupt acknowledge
o Acknowledges an interrupt request input applied to the INTR pin
- INTA
- MCE/PDEN
o Master cascade/peripheral data
