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CS 6291 Embedded Software > Lesson 4--Datapaths > Flashcards

Lesson 4--Datapaths Flashcards

1
Q

What is a datapath with respect to VLIW

A

the collection of its execution units, which performs data transformation

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2
Q

In these two RSA, all operands reside in memory

A

CISC and DSP

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3
Q

Where do operands reside in VLIW and RISC

A

Operands are in the registers before any work is done.

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4
Q

True or False: 16 bit buses are much more efficient than 32 bit buses

A

True

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5
Q

ISA minimum requirements

A
  • -Minimum commands for accessing memory ­ load, store
  • -Minimum commands to perform arithmetic functions ­ subtraction
  • -Minimum commands for control functions ­ less than zero, equals zero, branch unconditional
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6
Q

Choosing Operations tradeoffs

A
  • -Efficiency
  • -Performance
  • -Complexity
  • -Design
  • -Silicon cost
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7
Q

Other architectures

A

SIMD
MIMD
microSIMD

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8
Q

True or False: VLIW is more efficient than microSIMD for a media processor

A

False

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9
Q

True or False: For the same number of addressible registers, microSIMD holds more multimedia data than superscalar or VLIW.

A

True

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10
Q

True or False: microSIMD supports data parallelism, but at a much higher complexity of register ports

A

False

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11
Q

Min instructions for accessing memory

A
  • -Load a value from mem into register

- -Store a value from a register into mem

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12
Q

Min instructions set to perform arithmetic functions of a processor:

A

Subtract

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13
Q

Min instructions set to perform control functions of a processor:

A
  • -Result is zero
  • -Result is less than zero (no need for greater than zero)
  • -Branch unconditional (goto)
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14
Q

VLIW datapath

A

Collection of its execution units, which performs data transformation

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15
Q

CISC and DSP

A

All operands reside in memory

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16
Q

VLIW and RISC

A

Operands are in the registers before any work is done.

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17
Q

True or False: 16 bit buses are much more efficient than 32 bit buses

A

TRUE

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18
Q

Choosing Operation Repertoire tradeoffs

A
  • -Efficiency
  • -Performance
  • -Complexity
  • -Design
  • -Silicon cost
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19
Q

Other architectures

A
  • -SIMD
  • -MIMD
  • -microSIMD
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20
Q

True or False: VLIW is more efficient than microSIMD for a media processor

A

False

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21
Q

True or False: For the same number of addressible registers, microSIMD holds more multimedia data than superscalar or VLIW.

A

True

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22
Q

True or False: microSIMD supports data parallelism, but at a much higher complexity of register ports

A

False

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23
Q

Min instructions for accessing memory

A
  • -Load a value from mem into register

- -Store a value from a register into mem

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24
Q

Min instructions set to perform arithmetic functions of a processor:

A

Subtract

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25
Q

Min instructions set to perform control functions of a processor:

A
  • -Result is zero
  • -Result is less than zero (no need for greater than zero)
  • -Branch unconditional (goto)
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26
Q

What is the controller’s role in the Datapath

A

The controller makes sure
the data is latched properly into the buffer,
coordinates ALU operations, IO devices, and Memory
and checks for hazards.

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27
Q

CISC and DSP all the operands reside in memory. So there must be ______ to______operations and complex addressing modes.

A

Memory to memory

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28
Q

Accumulators are target registers of the ALU

A

This means the compiler is forced to make binding choices and optimizations too early to reduce the memory traffic.

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29
Q

True or false: VLIW and RISC use lost of registers

A

True

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30
Q

True or false: VLIW and RISC compiler does not need to be very aggressive with register allocation

A

False

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31
Q

True or false: VLIW and RISC compiler must decouple scheduling and register allocation. So first scheduling is performed, the register allocation is done.

A

True

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32
Q

Datapath Operations Cycles

A

The 32 bit processors take way more cycles than the 16 bit versions because the 32 bit operations break down the operations into 16 bit operations and use the carry bit to extend the size.

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33
Q

True or False: Datapath Operations Cycles that use 16 bit buses operate much less efficiently than 32 bit buses.

A

False

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34
Q

Datapath Width

A

The width of the datapath equals the width of the registers that hold int and float.

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35
Q

Datapath Width

A

The width of the datapath equals the width of the registers that hold int and float.

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36
Q

False

A

True or False: The initial versions for ARM supported floating point operations, was done through a software library.

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37
Q

True

A

True or False: The initial versions for ARM processors were extremely efficient, but the time for floating point operations was 100s of clock cycles

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38
Q

False, there was usually two

A

True or False: CISC and RISC usually have only one datapaths, each the width of the datapath.

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39
Q

Narrower

A

With CISC and RISC, the integer datapath is narrower or wider than the floating point one?

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40
Q

DSPs datapaths

A

These are likely to be 40 bits or 56 bits, these are ADC widths

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41
Q

8 - 32

A

VLIW Datapath Widths had __ to __ bit independent datapaths

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42
Q

True

A

True or False: VLIW Datapath Widths could be reconfigured to support floating point operations

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43
Q

Operation Repertoire

A

Choosing which operations to include in the ISA is difficult

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44
Q

Additional Operation Repertoire tradeoffs

A

–application analysis
–execution frequency
–implementation complexity
all must be considered for this operation

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45
Q

The characteristics of application domain are:

A
  • -Simple integer and compare operations for the basic units of execution of any program.
  • -datapaths are extremely important.
  • -In CISC Carry, Overflow, and other flags are set by the arithmetic operations
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46
Q

CISC

A

In CISC or RSIC: Overflow, and other flags are set by the arithmetic operations?

47
Q

VLIW

A

With CISC or VLIW: Which one has more than one arithmetic operations occurring at the same time?

48
Q

VEX

A

With VEX or VLIW: Where are flags stored in branch registers?

49
Q

large and slow

A

Are Multipliers small and fast or large and slow?

50
Q

smaller operations

A

Are VEX the multiplication is broken down into larger or smaller operations

51
Q

upper and lower

A

Integer Multiplication: The 32 bit multiplication is divided into two 16 bit multiplications? upper and lower or upper only or lower only?

52
Q

NOP and multiplication

A

Integer Multiplication: There is a NOP or Branch inserted to allow for the delay created with the multiplication or division?

53
Q

Fixed Point Multiplication

A

Most embedded systems need short fixedpoint to represent important data types

54
Q

In VEX there are 3 multiplication forms

A

In ____ there are 3 multiplication forms�low 16 * low 16, low 16 * high 16, high 16 * high 16 (number of bits)

55
Q

T/F: Higher precision fixedpoint multiplication is cheap

A

False, it is expensive

56
Q

True

A

True or False: Interger division is more expensive than multiplication?

57
Q

Integer Division is more complex

A

With this type math, it is more complex because the answer may be an integer or a FP value

58
Q

VEX

A

In ___, divs instruction is provided for basic component for an integer division.

59
Q

35 cycles

A

Nonrestoring 32bit division can take __ cycles

60
Q

Shorter and Constant

A

The compiler may optimize shorter or loger divisions or divisions by constants or varibles?

61
Q

code size

A

Division is rarely critical and many systems favor code size or code quality to hardware design.

62
Q

Saturated Arithmetic

A

This arithmetic occurs when you try to exceed the precision that is allowed for the implementation

63
Q

It becomes an an overflow ; the result is 0X00000000

A

What is the result if we add 1 to a a 32 bit int 0XFFFFFFFF wrap around?

64
Q

No

A

Are embedded domains overflows acceptable?

65
Q

What is used instead of embedded domains overflows?

A

Saturated arithmetic is used.

Example: 60 + 43 ? 100. (not the expected 103.)

66
Q

In SIMD or VLIW; instruction sets, the same instruction works on a large quantity of data?

A

SIMD

67
Q

In SIMD or VLIW; instruction sets, each instruction works on only one data set?

A

VLIW

68
Q

In SIMD or VLIW; can be multiple instructions and multiple data sets?

A

VLIW

69
Q

MicroSIMD Parallel Subword Architecture

A

With this Architecture, it has 64 bit FU can process words as 1 64 bit, 2 32 bit, or 4 16 bit

70
Q

microSIMD Parallel Subword Architecture

A

With this Architecture, data can be compacted and be fit into a long 64 bit word

71
Q

True or False: With microSIMD, data can be compacted and be fit into a long 64 bit word.

A

True

72
Q

It speeds up processing and reduces data size requirements

A

With microSIMD, it speeds up processing and reduces data size requirements or does it reduce processing and speed up
data size?

73
Q

MIMD

A

MIMD or SIMD has 4 instructions on 4 cores?

74
Q

SIMD

A

MIMD or SIMD operates on four different data items with one instruction?

75
Q

Superscalar

A

Superscalar or SIMD Operates on 4 instructions, four cores?

76
Q

VLIW

A

VLIW or Superscalar has one instruction, four sub operations?

77
Q

False; x86 are popular

A

True or False: MicroSIMD Operations are not popular

78
Q

MicroSIMD

A

In embedded systems MicroSIMD or VLIW manipulates subwords

79
Q

8 bits, 16 bits, 32 bits, 64 bits

A

MicroSIMD subwords are configurable bits of ___bits, ___bits, ___bits, ___bits

80
Q

False; They need small precision qualities

A

True or False: Multimedia applications usually need large precision quantities

81
Q

PADD4

A

PADD4 or 4PADD breaks down larger words into sub words. Then adds 4 sub words together. Then operate on the four sub words.

82
Q

False, they have difficulties.

A

True or False: In practice, microSIMD operations have no difficulties.

83
Q

microSIMD operations difficulties

A
  • -Alignment issues are a problem when breaking into subwords.
  • -Structures that contain subword elements rarely align cleanly to word boundaries.
  • -Unoptimized pre/post loop codes are needed.
  • -Precision Issues there may need to be a few extra bits for holding intermediate stages of an algorithm
84
Q

False, they have to respect control flow

A

True or false: MicroSIMD operations does not need to respect the control flow.

85
Q

MicroSIMD

A

MicroSIMD or VLIW must mimic existing branches

86
Q

Two operations control flow in MicroSIMD

A
  • -it must mimic existing branches extensions

- -include partial predication

87
Q

PCMPGT4

A

PCMPGT4 or PADD4; does the compare at a boundary. Then take the subwords on the integer boundaries do the add and subtraction. The PSELECT then
chose the branch to take.

88
Q

SIMD

A

The sequential program can be parallelized using VEX or SIMD?

89
Q

MicroSIMD

A

MicroSIMD or VLIW: The data is divided into subelements and then stored in a register. The entire register is operated on at the same time,
leading to 4 data points being operated on at the same time. Reducing the processing time of the operation.

90
Q

MicroSIMD

A

MicroSIMD or VLIW: Can achieve impressive results with a minimal hardware complexity

91
Q

False

A

True or False: complete set of microSIM extensions do not costs too much

92
Q

True

A

True or False: automatic extrications microSIMD w/o hints by the compiler is still unproven.

93
Q

False

A

With Manual code resturcturing is no longer needed to exploit micro SIMDparallelism

94
Q

True

A

True or False: microSIMD can pack more data than VLIW

95
Q

True

A

True or False: microSIMD holds more multimedia data then superscalar or VLIW architectures

96
Q

VLIW

A

The complexity of register ports is higher in VLIW or microSIMD?

97
Q

True or False: microSIMD is able to support a large number of operands.

A

True

98
Q

The number of register files is much less or more for microSIMD.

A

Less

99
Q

True or False: microSIMD is more powerful than MIMD, SIMD, VLIW

A

True

100
Q

True

A

True or False: VLIW can do four different kinds of instructions, while SIMD cannot.

101
Q

VLIW

A

VLIW or VEX is better for more general parallelism.

102
Q

Constants

A
  • -Specifically the immediate operands and literals.

- -Are known at compile time, others at load time.

103
Q

Short or Long immediate constants tend to be used in addressing modes and fit in a single encoded operation

A

Short

104
Q

Long

A

Short or Long immediate constants can be the width of the datapath.

105
Q

2

A

There are 2, 8 or 64 methods for long immediates

106
Q

Two methods for long immediates

A
  • -partial immediate load
  • -memory allocated immediate in this case the compiler allocates long immediate in memory and emits an instruction that loads the immediate. (emits?)
107
Q

True or False: With Constants Branch offsets are not immediate

A

False; They are immediate

108
Q

Constants

A

MIPS or VLIW have a jump instruction has 26 bit wide offsets.

109
Q

MIPS

A

PC is word aligned in MIPS or VLIW, so you can jump 28 bits.

110
Q

T/F: Most embedded processes are 32-bit ISAs include a branch offset large enough to cover local branches

A

True

111
Q

What are the special needs of datapaths to be supported in embedded computing?

A

find out.

112
Q

What are the minimum instructions for accessing memory?

A

load value from memory to register

store a value in a register to memory

113
Q

What the minimum instructions to perform the arithmetic functions of a processor?

A

subtract

114
Q

What is the minimum instruction set to perform the control functions of a processor?

A

result is zero
result is less than zero
branch conditional

CS 6291 Embedded Software (16 decks)

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