Lesson 2--Review of VLIW Flashcards
Describe the RISC Architecture
- -Simple, fewer instructions
- -Fixed length instructions
- -Complexity in compiler
- -Only LOAD/STORE instructions access memory
- -Few addressing modes
- -simpler hardware
- -lower per-chip cost
- -code expansion can be a problem
Describe the CISC Architecture
- -many complex instructions
- -variable length instructions
- -complexity in microcode
- -many instructions access memory
- -many accessing modes
- -makes more efficient use of a slow memory
- -requires less complicated compiler
- -instructions take different amounts of time to execute
VLIW Pros
Lots of registers
Lower number of transistors than other designs
Can take advantage of size efficiencies, price, power consumption
VLIW Cons
not backward compatible or easily upgradable
Instruction Scheduling: VLIW vs Superscalar
Superscalar: Done by hardware at run-time
VLIW: Done by compiler
Which parts of Superscalar and VLIW handle data dependency?
Superscalar: Checked and resolved by hardware
VLIW: Checked by compiler
The hardware of this architecture handles all register renaming
Superscalar
A high bandwidth between instruction cache and fetch unit
VLIW
The hardware of this architecture tries to issue as many instructions in parallel as possible
Superscalar
This architecture has larger power consumption.
Superscalar
In addition to the “normal compiler” tasks a VLIW compiler also includes
scheduling and operation
independence recognizing software
Which (RISC or CISC) requires more instructions for the same task
RISC
ISA stands for
Instruction Set Architecture
Explain the Front end role of a compiler
parses specific language
Explain the Middle role of a compiler
A machine independent high-level optimizer which creates an intermediate language independent form.
