Lesson 13--Storage Assignment Optimizations Flashcards

1
Q

Address register

A

Contains the address of the operand to fetch from memory

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2
Q

Auto increment mode

A

Get the operand and increment the same instruction. Reduces code size and improves efficiency.

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3
Q

Access Graph

A

A graph of the access sequence. Unlike an adjacency graph, directions are not material.

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4
Q

Access graph weight

A

Sum of the edges

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5
Q

Access graph cost

A

Sum of the weights of the edges in G but not in C, where C is the cover (no cycles and we can remove uncovered edges and the graph will still be connected).

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6
Q

MWPC

A

Maximum weight per cover

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7
Q

Single Offset Assignment

A

–Every data object has a size of one word
­–A single address register AR) is used to address all variables. Auto increment and decrement are used to transition
­–One-­to-­one mapping of variables to locations
­–The basic block has a fixed evaluation order (schedule).

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8
Q

General Offset Assignment

A

–K address registers Ar0­AR(k­1)
­–Given access sequence L, set of variables V number of address registers k
­–Find a partition of V, where m <= k.
­–Such that the total cost of the optimal SOA of the corresponding access subsequences plus the setup cost for using the m register is minimal.

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9
Q

Relax fixed evaluation order assumption

A

Transform the access sequence using algebraic properties to change the access order

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10
Q

Variable coalescence

A

Putting two variables into the same memory location

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11
Q

Coalesced Node (C-Node)

A

A set of live ranges in the AG or IG that are coalesced

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12
Q

Coalesced Edge (C-Edge)

A

An edge set defined for a pair of C-Nodes

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13
Q

Coalesced Access Graph (C-AG)

A

The AG after coalescence

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14
Q

Coalesced IG (C-IG)

A

The IG after node coalescence

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15
Q

Coalesced Path Cover (C-PC)

A

On a C-AG, a C-PC consists of a sequence

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