Lesson 1--Review of Computer Architecture

Question 1

Instruction Level Parallelism (ILP)

Answer 1

• -Executes multiple operations simultaneously in a given cycle.
• -Program’s property. # of instructions exectuted per cycle depends on the program.
• -Independent of hardware

Question 2

Low Instructions Per Cycle (IPC) is a result of…

Answer 2

• -strict sequential semantics

- -instructions stalled for data or resource release by other instructions

Question 3

Pipelining

Answer 3

Used to overlap instructions

Question 4

Pipelines in modern CPUs have the following characteristics

Answer 4

• -execution stages are divided into several steps
• -a later operation can share the resources used by the first operation in previous cycles
• -shared hardware can be pipelined

Question 5

Given a programs function unit cycles and the percentage of program’s percentage of instructions using each function unit how would the Cycles Per Instruction (CPI) be calculated?

Answer 5

((FU1cycles x FU1percentage) + (FU2cycles x FU2percentage) + (FU3cycles x FU3percentage) + …)/100

Question 6

For a pipeline that is k stages deep, how many cycles does it take to fill the pipeline?

Answer 6

k - 1

Question 7

VLIW stands for.

Answer 7

Very Long Instruction Word

Question 8

How many operations can a VEX processor have in each cycle using VLIW?

Answer 8

4

Question 9

In a VEX processor, what are the requirements for the instructions in a single word?

Answer 9

­ –cannot have dependencies
­ –cannot share resources
­ –only one memory access per word

Question 10

Read After Write (RAW)

Answer 10

True dependency

Question 11

Write After Write (WAW)

Answer 11

False dependency

Question 12

Write After Read (WAR)

Answer 12

False dependency

Question 13

3 Minimizing Dependencies Techniques

Answer 13

• -Branch prediction/ Speculation
• -Predication
• -Register Renaming

Question 14

Branch prediction

Answer 14

Predict which branch might be taken

Question 15

Predication

Answer 15

Use conditional moves

execute all the branch condition’s statements, but don’t commit them to memory until the branch conditions are known

Question 16

Register Renaming

Answer 16

Used to avoid WAW and WAR dependencies

Question 17

What are the key performance metrics for Embedded Processors

Answer 17

• High Performance
• Low Cost
• Low Energy Consumption

Question 18

Which processors would be good for embedded processors?

• Superscalar, out of order
• Superscalar, in order
• VLIW, in order
• VLIW, out of order

Answer 18

VLIW, in order

because multiple instructions in a slot lead to better performance with the most energy efficient solution.

Question 19

How is clock frequency related to energy

Answer 19

1/e -> f^2

Question 20

How deep are the pipelines in modern high performance processors?

• 5 to 7 stages
• 8 to 10 stages
• 15 to 20 stages
• 100+ stages

Answer 20

15 to 20 stages

Question 21

WhatistheCPI?

MIPSmachine:
Aloadtakes5cycles
Astoretakes4cycles
AnR­typeinstructiontakes4cycles
Branchtakes3cycles
Jumptakes3cycles

For a program,
50%R­type,
10%load,
20%store,
8%branch,
29%jumpinstructions

Answer 21

R­typeinstructions:4cycles,50%=450
loadinstructions:5cycles,10%=510
storeinstructions:4cycles,20%=420
branchinstructions:3cycles,8%=38
jumpinstructions:3cycles,2%=3*2

CPI=(450+510+420+38+3*2)/100=3.6

Question 22

What are the 5 stages of a basic pipeline execution model?

Answer 22

Fetch - get the next instruction
Decode - figure out what that instruction is
Execute - perform ALU, or address calc in mem op
Memory - mem access if necessary
WriteBack- write the result back

Question 23

What is control dependence

Answer 23

whether or not to execute an instruction or a group of instructions based on control flow conditions (if, else)

Question 24

List three types of Data dependence

Answer 24

Read after write
Write after write
Write after Read

Question 25

Other parallelisms in available for computing systems

Answer 25

Vector processing
Multithreading, multiprocessing
Micro-SIMD