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Microprocessors > Chapter 9 > Flashcards

Chapter 9 Flashcards

1
Q

Where are 8086 and 8088 microprocessors packaged in?

A

dual in-line packages (DIPs)

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2
Q

How many pins does dual in-line packages have?

A

40

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3
Q

contain the rightmost 8 bits of the memory address or I/O port number whenever ALE is active or data whenever ALE is inactive.

A

AD7-AD0; Address/Data Bus

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4
Q

provides the upper-half memory address bits that are present throughout a bus cycle

A

A15-A8; Address Bus

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5
Q

Compose the upper multiplexed
address/data bus on the 8086

A

AD15-AD8; address/data bus

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6
Q

Are multiplexed to provide address signals A19-A16 and also status bits S6-S3.

A

A19/S6-A16/S3; address/status bus

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7
Q

Whenever ____ is a logic 0, the data bus is receptive to data from the memory or I/O devices connected to the system.

A

R̅D̅; read signal

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8
Q

is controlled to insert wait states into the timing of the microprocessor.

A

READY

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9
Q

used to request a hardware interrupt

A

INTR; Interrupt Request

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10
Q

Is an input that is tested by the WAIT instruction

A

T̅E̅S̅T̅

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11
Q

INTA

A

Interrupt Acknowledge

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12
Q

Is similar to INTR except that it does not check to see whether the IF flag bit is logic 1

A

Non-Maskable Interrupt (NMI)

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13
Q

causes the microprocessor to reset itself if this pin is held high for a minimum of four clocking periods

A

RESET

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14
Q

provides the basic timing signal to the microprocessor

A

Clock (CLK)

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15
Q

provides a +5.0 V, ±10 % signal to the microprocessor

A

Voltage Common Collector (VCC)

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16
Q

is the return for the power supply

A

Ground (GND)

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17
Q

selects either minimum mode or maximum mode operation for the microprocessor

A

Minimum/Maximum (MN/M̅X̅)

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18
Q

used in the 8086 to enable the most-significant data bus bits (D15–D8) during a read or a write operation

A

Bus High Enable (B̅H̅E̅ S7)

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19
Q

is obtained by connecting
the MN/M̅X̅ pin directly to +5.0 V

A

Minimum Mode Pins

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20
Q

This pin indicates that the microprocessor address bus contains either a memory address or an I/O port address

A

IO/M̅ or M/I̅O̅

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21
Q

is a strobe that indicates that the 8086/8088 is outputting data to a memory or I/O device

A

Write Line (W̅R̅)

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22
Q

is normally used to gate the interrupt vector number onto the data bus in response to an interrupt request

A

I̅N̅T̅A̅

23
Q

shows that the 8086/8088 address/data bus contains address information

A

Address Latch Enable (ALE)

24
Q

shows that the microprocessor data bus is transmitting or receiving data

A

Data Transmit/Receive (DT/R̅)

25
Q

activates external data bus buffers

A

Data Bus Enable (DEN)

26
Q

If the ____ signal is a logic 1, the microprocessor stops executing software and places its address, data, and control bus at the high-impedance state, if it is a logic 0, the microprocessor executes software normally.

A

HOLD

27
Q

Indicates that the 8086/8088 has entered the hold state

A

Hold Acknowledge (HLDA)

28
Q

This signal is combined with IO/M̅ and DT/R̅ to decode the function of the current bus cycle

A

Single Sign-on (S̅S̅0̅)

29
Q

is obtained by connecting the MN/M̅X̅ pin to ground

A

Maximum Mode Pins

30
Q

indicate the function of the current bus cycle

A

Status Bits (S̅2̅, S̅1̅, and S̅0̅)

31
Q

request direct memory accesses during maximum mode operation

A

Request/Grant
(R̅Q̅/G̅T̅1̅ and R̅Q̅/G̅T̅0̅)

32
Q

is used to lock peripherals off the system

A

L̅O̅C̅K̅

33
Q

show the status of the internal instruction queue

A

Queue Status (QS₁ and QS₀)

34
Q

is an ancillary component to the 8086/8088 microprocessors

A

8284A Clock Generator

35
Q

are provided to qualify the bus ready signals, RDY1 and RDY2, respectively

A

Address Enable (A̅E̅N̅1̅ and A̅E̅N̅2̅)

36
Q

are provided, in conjunction with the A̅E̅N̅1̅ and A̅E̅N̅2̅ pins, to cause wait states in an 8086/8088-based system

A

Bus Ready (RDY1 and RDY2)

37
Q

selects either one or two stages
of synchronization for the RDY1 and RDY2 inputs

A

Ready Synchronization (A̅S̅Y̅N̅C̅)

38
Q

an output pin that connects to the 8086/8088 READY input

A

READY

39
Q

connect to an external crystal used as the timing source for the clock generator and all its functions

A

Crystal Oscillator (X1 and X2)

40
Q

chooses the clocking source for the
8284A

A

Frequency Crystal (F/C̅)

41
Q

provides the CLK input signal to the 8086/8088 microprocessors and other components in the system

A

Clock Output (CLK)

42
Q

is one sixth the crystal or EFI input frequency, and has a 50% duty cycle

A

Peripheral Clock (PCLK)

43
Q

is a TTL-level signal that is at the same frequency as
the crystal or EFI input

A

Oscillator Output (OSC)

44
Q

is often connected to an RC network that provides power-on resetting

A

Reset Input (R̅E̅S̅)

45
Q

is connected to the 8086/8088 RESET input pin

A

Reset Output (RESET)

46
Q

is used whenever the EFI input provides synchronization in systems with multiple processors

A

Clock Synchronization (CSYNC)

47
Q

connects to the ground

A

GND

48
Q

connects to +5.0 V with a tolerance of ±10%

A

Power Supply (VCC)

49
Q

If more than 10 unit loads are attached to any bus pin, the entire 8086 or 8088 system must be _____

A

buffered

50
Q

provides the memory and I/O with the memory address or the I/O port number

A

Address Bus

51
Q

transfers data between the microprocessor and the memory and I/O in the system

A

Data Bus

52
Q

provides control signals to the memory and I/O

A

Control Bus

53
Q

i an extra clocking period, inserted between T2 and T3 to lengthen the bus cycle

A

Wait State (Tw)

Microprocessors (28 decks)

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