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Microprocessors > Chapter 11 > Flashcards

Chapter 11 Flashcards

1
Q

o transfers information to an I/O device

A
  • OUT
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2
Q

o read information from an I/O device

A
  • IN
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3
Q

o 8-bit form (p8)

A
  • fixed address
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4
Q

o 16 bit I/O address

A
  • Variable address
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5
Q

o the I/O address

A
  • Port number
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6
Q
  • ISA
A

o industry standard architecture

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7
Q

o most common I/O transfer technique used in the Intel microprocessor-based system

A
  • isolated I/O
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8
Q

o does not use the IN, INS, OUT, or OUTS instructions

A
  • Memory-Mapped I/O
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9
Q

o uses any instruction that transfers data between the microprocessor and memory

A
  • Memory-Mapped I/O
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10
Q

o Three-state buffers are used to construct the 8-bit input port

A
  • Basic Input Interface
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11
Q

o receives data from the microprocessor and usually must hold it for some external device.

A
  • Basic Output Interface
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12
Q

o Also called polling

A
  • Handshaking
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13
Q

o synchronizes the I/O device with the microprocessor

A
  • Handshaking
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14
Q

o Are TTL and compatible, and therefore can be connected to the microprocessor and its interfacing components, or they are switch-based

A
  • Input Devices
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15
Q

o are far more diverse than input devices, but many are interfaced in a uniform manner

A
  • Output Devices
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16
Q

o programmable peripheral interface

A
  • PPI
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17
Q

o very popular, low-cost interfacing component found in many applications

A
  • PPI
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18
Q

o can interface any TTL-compatible I/O device to the microprocessor

A
  • 82C55
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19
Q

o have replaced LED displays in many applications

A
  • LCD
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20
Q

o a digital motor because it is moved in discrete steps as it traverses through 360°

A
  • stepper motor
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21
Q

o This allows external data to be stored into the port until the microprocessor is ready to retrieve it

A
  • Mode 1 Strobed Input
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22
Q

o loads data into the port latch, which holds the information until it is input to the microprocessor via the IN instruction

A
  • STB
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23
Q
  • STB
A

o Strobe

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24
Q

o an output indicating that the input latch contains information

A
  • IBF
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25
Q
  • IBF
A

o Input buffer full

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26
Q

o an output that requests an interrupt

A

o Interrupt request

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27
Q
  • INTE
A

o interrupt enable

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28
Q

o is neither an input nor an output; it is an internal bit programmed via the port PC4 (port A) or PC2 (port B) bit position

A
  • INTE
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29
Q

o The port C pins 7 and 6 are general-purpose I/O pins that are available for any purpose.

A
  • PC7, PC6
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30
Q

o strobed input device

A
  • Keyboard
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31
Q

o an output that goes low whenever data are output (OUT) to the port A or port B latch

A
  • OBF
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32
Q
  • OBF
A

o Output buffer full

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33
Q

o causes the pin to return to a logic 1 level. The signal is a response from an external device, indicating that it has received the data from the 82C55 port

A
  • ACK
34
Q
  • ACK
A

o acknowledge signal

35
Q

o a signal that often interrupts the microprocessor when the external device receives the data via the ACK signal.

A
  • INTR
36
Q
  • INTR
A

o Interrupt request

37
Q

o is neither an input nor an output; it is an internal bit programmed to enable or disable the INTR pin

A
  • INTE
38
Q

o strobe data into the printer

A
  • DS
39
Q
  • DS
A

o Data strobe

40
Q

o an output used to interrupt the microprocessor for both input and output conditions.

A
  • INTR
41
Q

o an output indicating that the output buffer contains data for the bidirectional bus

A
  • OBF
42
Q

o an input that enables the three-state buffers so that data can appear on port A

A
  • ACK
43
Q

o loads the port A input latch with external data from the bidirectional port A bus

A
  • STB
44
Q

o an output used to signal that the input buffer contains data for the external bidirectional bus

A
  • IBF
45
Q

o are internal bits (INTE1 and INTE2) that enable the INTR pin

A
  • INTE
46
Q

o These pins are general-purpose I/O pins in mode 2 controlled by the bit set and reset command

A
  • PC0, PC1, PC2
47
Q
  • A0, A1
A

o Address inputs

48
Q

o select one of four internal registers within the 8254

A
  • A0, A1
49
Q

the timing source for each of the internal counters

A
  • CLK
50
Q

o enables the 8254 for programming and reading or writing a counter

A
  • CS
51
Q

o controls the operation of the counter in some modes of operation

A
  • G
52
Q
  • G
A

Gate

53
Q

o connects to the system ground bus

A
  • GND
54
Q

o counter output

A
  • OUT
55
Q

o where the waveform generated by the timer is available

A
  • OUT
56
Q

o causes data to be read from the 8254 and often connects to the IORC signal

A
  • RD
57
Q
  • RD
A

o Read

58
Q

o Connects to the +5.0V power supply

A
  • Vcc
59
Q

o causes data to be written to the 8254 and often connects to the write strobe IOWC

A
  • WR
60
Q

o Allows the 8254 counter to be used as an events counter

A
  • MODE 0
61
Q

o Causes the counter to function as a retriggerable, monostable multivibrator

A
  • MODE 1
62
Q

o Allows the counter to generate a series of continuous pulses that are one clock pulse wide

A
  • MODE 2
63
Q

o Generates a continuous square wave at the OUT connection, provided that the G pin is a logic 1

A
  • MODE 3
64
Q

o Allows the counter to produce a single pulse at the output

A
  • MODE 4
65
Q

o A hardware triggered one-shot that functions as mode 4, except that it is started by a trigger pulse on the G pin instead of by software

A
  • MODE 5
66
Q

o programmable communications interface designed to connect to virtually any type of serial interface

A
  • PC16550D
67
Q

o transmitted and received without a clock or timing signal

A
  • Asynchronous Serial Data
68
Q

PLCC

A

o Plastic leadless chip carrier

69
Q

FM

A

o Frequency modulation

70
Q

CB

A

o Citizens band

71
Q

o address inputs are used to select an internal register for programming and also data transfer

A
  • A0, A1, A2
72
Q
  • ADS
A

o Address strobe

73
Q

o used to latch the address lines and chip select lines

A
  • ADS
74
Q

o where the clock signal generated by the baud rate generator from the transmitter section is made available

A
  • BAUDOUT
75
Q

o must all be active to enable the 16550 UART

A
  • CS0, CS1, CS2
76
Q

o indicates that the modem or data set is ready to exchange information

A
  • CTS
77
Q
  • CTS
A

o Clear to send

78
Q

o received data contain the wrong parity

A
  • parity error
79
Q

o start and stop bits are not in their proper places

A
  • framing error
80
Q

o data have overrun internal receiver FIFO buffer

A
  • overrun error

Microprocessors (28 decks)

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