4.1. Central Processing Unit Architecture Flashcards

1
Q

Von Neumann model

A
  • Von Neumann realized data & programs are
    indistinguishable and can therefore use same
    memory.
  • Von Neumann architecture uses a single processor.
  • It follows a linear sequence of fetch–decode–execute
    operations for the set of instructions i.e. the program.
    In order to do this, the processor uses registers.
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2
Q

Define Registers

A

Smallest unit of storage of microprocessor;
allows fast data transfer between other registers

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3
Q

General Purpose registers

A
  • Used to temporarily store data values which have
    been read from memory or some processed result
  • Can be used by assembly language instructions
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4
Q

Special Purpose Registers

A
  • Some are accessible by assembly language
    instructions
  • Only holds either data or memory location, not both
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5
Q

Special purpose registers include

A
  • Program Counter (PC): holds address of next
    instruction to be fetched
  • Memory Data Register (MDR): holds data value
    fetched from memory
  • Memory Address Register (MAR): Holds address of
    memory cell of program which is to be accessed
  • Accumulator (ACC): holds all values that are
    processed by arithmetic & logical operations.
  • Index Register (IX): Stores a number used to
    change an address value
  • Current Instruction Register (CIR): Once program
    instruction fetched, it is stored in CIR and allows
    the processor to decode & execute it
  • Status Register: holds results of comparisons to
    decide later for action, intermediate and
    erroneous results of arithmetic performed
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6
Q

The Processor (CPU)

A
  • Arithmetic and Logic Unit (ALU): part of processor that
    processes instructions which require some form of
    arithmetic or logical operation
  • Control Unit (CU): part of CPU that fetches
    instructions from memory, decodes them &
    synchronizes operations before sending signals to
    computer’s memory, ALU and I/O devices to direct
    how to respond to instructions sent to processor
  • Immediate Access Store (IAS): memory unit that can
    be directly accessed by the processor
  • System Clock: timing device connected to processor
    that is needed to synchronize all components.
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7
Q

Buses

A

Set of parallel wires that allow the transfer data
between components in a computer system

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8
Q

Data bus

A

Bidirectional bus that carries data
instructions between processor, memory, and I/O
devices.

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9
Q

Address bus

A

Unidirectional bus that carries
address of main memory location or input/output
device about to be used, from processor to
memory address register (MAR)

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10
Q

Control bus

A
  • Bidirectional and unidirectional
  • Used to transmit control signals from control unit
    to ensure access/use of data & address buses by
    components of system does not lead to conflict
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11
Q

Performance of Computer System Factors

A

Clock Speed, Bus Width, Cache Memory, Number of Cores

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12
Q

Clock Speed

A
  • Number of pulses the clock sends out in a given
    time interval, which determines the number of
    cycles (processes) CPU executes in a given time
    interval
  • Usually measured in Gigahertz (GHz)
  • If the clock speed is increased, then execution
    time for instructions decreases. Hence, more
    cycles per unit time, which increases performance.
  • However, there is a limit on clock speed since the
    heat generated by higher clock speeds cannot be
    removed fast enough, which leads to overheating
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13
Q

Bus Width

A
  • Determines number of bits that can be
    simultaneously transferred
  • Refers to number of lines in a bus
  • Increasing bus width increases number of bits
    transferred at one time, hence increasing
    processing speed and performance since there
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14
Q

Cache Memory

A
  • Commonly used instructions are stored in the
    cache memory area of the CPU.
  • If cache memory size is increased, more
    commonly executed instructions can be stored
    and the need for the CPU to wait for instructions
    to be loaded reduces, hence CPU executes more
    cycles per unit time, thus improving performance
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15
Q

Number of Cores

A
  • Most CPU chips are multi-core — have more than
    one core (essentially a processor)
  • Each core simultaneously processes different
    instructions through multithreading, improving
    computer performance
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16
Q

Ports

A
  • Hardware which provides a physical interface
    between a device with CPU and a peripheral device
  • Peripheral (I/O) devices cannot be directly connected
    to CPU, hence connected through ports
  • Universal Serial Bus (USB): Can connect both input
    and output devices to processor through a USB port
  • High Definition Multimedia Interface (HDMI)
  • Can only connect output devices (e.g. LCD display)
    to the processor through a HDMI port
  • HDMI cables transmit high-bandwidth and highresolution video & audio streams through HDMI
    ports
17
Q

Video Graphics Array (VGA)

A
  • Can only connect output devices (e.g. second
    monitor/display) to the processor through a VGA
    port
  • VGA ports allows only the transmission of video
    streams, but not audio components
18
Q

Fetch-Execute (F-E) cycle

A
  • Fetch stage
  • Decode stage
  • Execute stage
19
Q

Fetch stage

A
  • PC holds address of next instruction to be fetched
  • Address in PC is copied to MAR
  • PC is incremented
  • Instruction loaded to MDR from address held in MAR
  • Instruction from MDR loaded to CIR
20
Q

Decode stage

A
  • The opcode and operand parts of
    instruction are identified
21
Q

Execute stage

A
  • Instructions executed by the control
    unit sending control signals
22
Q

Register Transfer Notation (RTN)

A
  • MAR ← [PC]
  • PC ← [PC] + 1
  • MDR ← [[MAR]]
  • CIR ← [MDR]
  • Decode
  • Execute
  • Return to start
  • Square brackets: value currently in that register
  • Double square brackets: CPU is getting value
    stored at the address in the register
23
Q

Interrupts

A
  • A signal from a program seeking processor’s attention
  • Interrupt Service Routine (ISR):
  • Handles the interrupt by controlling the processor
  • Different ISRs used for different sources of
    interrupt
24
Q

Typical sequence of actions when interrupt occurs

A
  • The processor checks interrupt register for interrupt
    at the end of the F-E cycle for the current instruction
  • If the interrupt flag is set in the interrupt register, the
    interrupt source is detected
  • If interrupt is low priority: then interrupt is disabled
  • If interrupt is high priority:
  • All contents of registers of the running process are
    saved on the stack
  • PC is loaded with the ISR, and is executed
  • Once ISR is completed, the processor restores
    registers’ contents from the stack, and the
    interrupted program continues its execution
  • Interrupts re-enabled and
  • Return to start of cycle