von neumann architecture Flashcards

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1
Q

von neumann architecture

A

the design upon which many general purpose computers are based. This architecture uses the stored program concept

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2
Q

how are data and instructions stored

A

as binary digits

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3
Q

where are data and instructions stored?

A

in the RAM

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4
Q

where are instructions fetched from, and how?

A

they are fetched from memory, one at a time (serially)

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5
Q

what does the processor do?

A

it decodes and executes an instruction, before cycling around to fetch the next instruction

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6
Q

when does the cycle stop?

A

until there are no more instructions available

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7
Q

what are the key elements of von neumann architecture

A
  1. data and instruction turned into binary
  2. data and instructions stored in RAM
  3. instructions fetched from memory serially
  4. processor decodes and executes instruction before fetching the next one
  5. cycle continues until instructions are finished
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8
Q

what are the 5 special registers that a processor uses when processing

A
  1. program counter
  2. MAR
  3. MDR
  4. CIR
  5. ACC
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9
Q

program counter

A

holds the memory address of the next instruction to be fetched from main memory

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10
Q

MAR

A

memory address register- holds the address of the current instruction that is to be fetched from the memory

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11
Q

MDR

A

memory data register- holds the contents found at the address held in the MAR, or data which is to be transferred to main memory

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12
Q

CIR

A

current instruction register- holds the instruction that is currently being decoded and executed

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13
Q

ACC

A

accumulator- holds the results of processing

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14
Q

the fetch-decode-execute cycle

A

the cycle that the central processing unit follows from boot-up until the computer has shut down in order to process instructions

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15
Q

steps of the fetch-decode-execute cycle

A
  1. the memory address held in the program counter is copied into the MAR
  2. the address in the program counter is then incremented - or increased - by one. The program counter now holds the address of the next instruction to be fetched
  3. the processor sends a signal containing the address of the instruction to be fetched along the address bus to the computers memory
  4. the instruction held in the memory address is sent along the data bus to the MDR
  5. the instruction held in the MDR is copied into the CIR
  6. the instruction held in the CIR is decoded and then executed. The results of processing are stored in the ACC
  7. the cycle then returns to step one
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16
Q

additional steps may be taken depending on the type of instruction,
if the instruction is to transfer data held in the ACC back to the RAM:

A

the intended memory address is copied into the MAR. The data to be transferred is copied into the MDR and then transferred to the specified address using the address bus data bus.