VHDL

Question 1

How do we always begin a VHDL code?

Answer 1

By defining the libraries that will be used. e.g. library IEEE; use IEEE.std_logic_1164.all;

Question 2

What is an entity?

Answer 2

The entity is equivalent to the symbol schematic design. It provides the name of the circuit and its interfaces.

(In the digital design project, the signals defined in entity represented signals (or PORTS) that were shared between two codes which were manipulated to get the FPGA to function accordingly).

Question 3

What does the architecture represent?

Answer 3

The architecture contains the behaviour of the circuit.

architecture structural of circuit1

BEGIN

–code for circuit behaviour, e.g. gate logic

END:

Question 4

What are the direction that a port can have?

Answer 4

In, out and inout.

• in = input
• out = output
• inout = bidirectional

Question 5

Where are the ports defined?

Answer 5

In the entity

Question 6

What is a port type?

Answer 6

A port type is defined for each port (input/output) in the entity, and describes the format of the information.

Question 7

What is the standard port type for a single bit?

Answer 7

std_logic

Question 8

What is a std_logic_vector?

Answer 8

A standard logic vector is the standard type for a one dimensional array.

Question 9

How do we define a standard logic vector which contains 8 bits?

Answer 9

std_logic_vector(7 downto 0)

Question 10

What are the values that a std_logic vector can have?

Answer 10

• ‘U’ - Uninitialised
• ‘X’ - Forcing unknown
• ‘0’ - Forcing 0
• ‘1’ - Forcing 1
• ‘Z’ - High impedance
• ‘W’ - Weak Unknown
• ‘L’ - Weak 0
• ‘H’ - Weak 1
• ’-‘ - Don’t care

Question 11

How is code in the architecture evaluated?

Answer 11

In parallel, (concurrency) this means that the statements/process within the architecture are evaluated at the statement rather than one after another.

Question 12

How is a process statement evaluated?

Answer 12

When a signal is the sensitivity list has made a transition which causes the process to be evaluated.

This is done sequentially, this means the statements are evaluated one after another like in software programming e.g. in C or python

Question 13

What do we use to represent a wire?

Answer 13

signal

Question 14

What is meant by a structural coding style?

Answer 14

Structural is a label that helps to idenitfy the coding style within the architecture.

The structural coding style refers to describing a design using module instances, such as lower-level building blocks like AND gates and flip-flops

Question 15

What is a behavioural coding style?

Answer 15

The architecture is defined to be structural.

This means that the code within the architecture uses only process statements.

Question 16

What is a sensitivity list?

Answer 16

The sensitivity list specified the set of objects (input, signals) that force the process statement to be evaluated. This occurs after a transition on a signal in the sensitivity list.

Question 17

What is a the difference between a signal and a variable?

Answer 17

Variable is an object that can hold a value, they are similar to signals but they do not have direct physical significance.

The main difference is that a signal is an object with past history of values, while a variable is an object with a single current value.

Variables can only be used within processes, e.g. to create an algorithm within a process, whereas signals are more flexible.

Variables are defined := and signals are defined using : only

Question 18

What is the two-process rule?

Answer 18

One combinatorial and one sequential process in one file.

Question 19

What is a coding difference between a combinational process and a sequential process?

Answer 19

A combinational process does not require a clock, it would only require the relevant signals or ports in the sensitivity list.

A sequential process requires a clock, this means that the sensitivity list includes clk

Question 20

What can case statements be used for?

Answer 20

To generate multiplexers

To create a FSM

Question 21

What is an inferred latch?

Answer 21

Latches are inferred in VHDL by using an IF statement without its matching ELSE. The signal is held at this value since no other instruction is given hence the signal is latched.

Question 22

What is the issue with inferred latches?

Answer 22

They can causes issues when synthesising e.g. in FPGA design.

They can impact timing

Question 23

How can we remove latches?

Answer 23

We can must assign both values of the if-else statement.

We can assign a statement to be a value other than 1/0 such as:

in a CASE statement

when others => null;

Question 24

Describe a hierarchical design

Answer 24

• Larger components are built using smaller components.
• Component declaration followed by component instantiation.
• Internal signals are used to connect components together.

Question 25

What kind of logic is a register?

Answer 25

Sequential