Exam

Question 1

Draw a diagram for a 20-bit carry bypass adder, that uses 4-bit ripple carry adders

Answer 1

Question 2

Draw the gate implementation of a full-adder

Answer 2

Question 3

Describe the critical path for worst case delay of 20-bit carry bypass adder that uses ripple carry in local carry chain

Answer 3

The critical path is:

1. Bit 0 - 3: Setup –> Local Carry Chain –> MUX
2. Bit 4 - 7: MUX
3. Bit 8 - 11: MUX
4. Bit 12 - 15: MUX
5. Bit 16 - 19: Local Carry Chain –> Sum (MUX/C_OUT ignored)

Question 4

Draw block diagram for 4-bit CLA adder

Answer 4

Question 5

What is the delay of the square-root adder?

Answer 5

Tadd ≈ Tsetup + 2*Tcarry + √ (2*N)*Tmux + Tsum

Question 6

How do we do a two-level SOP minimisation?

Answer 6

1. Draw a Karnaugh map
2. Loop all prime implicants
3. Identify the essential prime implicants, which are prime implicants that can only be included in one loop and must be included in the SOP
4. Minimise number of Second-level gate inputs which are number of prime implicants used
5. Minimise number of First-level gate inputs which are number of variables in a single prime implicant

Question 7

How do we find MEV that appear the least in a two-level SOP?

F(A,B,C,D,E,F) = B′D′E′+ABD′E′+DEF+B′E′+BD′E′+B′C′D′E.

Answer 7

The variables that appear the least are the sum products that have the least number of variables

A,C and F only appear once in function

DEF = will likely produce 4 variables as DE will produce 4

B′C′D′E = C will appear less than F

ABD’E = A will appear less than F

Question 8

How do we form a multiplexer from a SOP?

Answer 8

Form a Karnaugh map for the function with the control inputs at the top (rows) and the remaining values on the bottom (columns)