Sequential Logic Design Flashcards

1
Q

In general, what do the outputs of a digital system depend on?

A

The outputs of a digital system depend on the current inputs and the history of the input up to the current time.

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2
Q

What is a defining attribute of sequential logic?

A

Sequential logic has storage (memory)

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3
Q

What is the purpose of storage elements in sequential logic?

A

Storage elements maintain the state of the circuit

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4
Q

List typical sequential circuits

A
  • Counters
  • Memories
  • Shift registers
  • Finite State Machines (FSM)
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5
Q

What are the main two types of sequential circuits?

A
  • Asynchronous
  • Synchronous
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6
Q

What is meant by an asychronous sequential circuit?

A

State transitions are triggered by primary input changes.

When the input changes, the circuit will react to the change without requiring a clock event.

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7
Q

How is an asynchronous sequential circuit implemented?

A

An asychronous circuit require delays, this is implemented using special delay elements or simply relies on propagation delays in the combinational logic elements

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8
Q

What is meant by a synchronous circuit?

A

State transitions are triggered by regular clock events.

We can say that changes in the state of memory elements are synchronised by a clock signal.

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9
Q

What is a D-type latch?

A

A variation of the S-R latch which is provided a delay by the introduction of D.

–EDIT–

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10
Q

What are the two models for a FSM?

A
  • Mealy machine
  • Moore machine
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11
Q

What is a Mealy machine?

A

A FSM in which the outpu depends on inputs and the current state.

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12
Q

What is a Moore machine?

A

A FSM in which the output depends only on the current state.

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13
Q

Describe the layout of a Mealy machine.

A
  • The states are contained in circles.
  • The arrows show how the state changes.
  • Each state will have arguments that cover all the possible arguments that may occur
  • The numbers shown by the arrows represent inputs/outputs (e.g. 1/0 = input 1/output 0)
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14
Q

How is a Mealy machine implemented in VHDL?

A
  1. Input and output ports, and their types are defined in entity mealy_machine
  2. In the architecture we define the two states as type state_type (state1, state2)
  3. In the architecture we define the signals current_state and next_state: state_type
  4. We define a sequential part which defines default value and the clock change-state change control
  5. Begin architecture - a case statement is used to define what we want to happen in each state
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15
Q

Describe the layout of a Moore machine

A
  • The states and their outputs are defined in circles
  • e.g. when a/0, b/1 = statea output0, stateb output1
  • Arrows show the combinations of inputs but not the output unlike Mealy machine
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16
Q

What is an important state that should be added to a CASE statement and why?

A

It is important to add the state:

when others => null;

This stops the circuit from going into an unknown state.