The Hardware/Software Interface Flashcards
DEFINE: Abstraction
The use of simple calls to replace complex processes from the high-level developer or user.
What are the three levels of the computer? What languages or processors do they utilize?
Applications software: Written in a high-level language (C, Python…)
System software: Assembly and machine code (binary)
Hardware: Not code, processors, memory, and I/O controllers
DEFINE: ISA
Instruction Set Architecture. The abstraction between hardware and software.
TRUE/FALSE: An ISA needs to be adjusted for every computer.
FALSE. As long as two computers have the same architecture, they can both run the same ISA.
What are the three levels of program code? In RISC-V, what language do they use?
High-level language: C
Assembly language: Assembly for RISC-V
Hardware representation: Binary
How many bytes do RISC-V instructions take up?
4 bytes (32 bits also OK)
Even today, what is Intel’s biggest selling point in regards to its processors?
Backwards Compatability
What three important criteria do we want to focus on when designing a “good” ISA?
High performance, power efficiency, and low cost
Why can Apple design “more efficient” chips than Intel, ARM, or NVIDEA?
They design their chips for their own software, so they can focus on the areas they need.
Against what is performance measured by?
Execution time (for a process, function, application, etc. Software).
DEFINE: CPU Time
Time spent by the processor on a given job. Ignores anything else (such as I/O, other threads)
What’s an equation that expresses the relation between clock period and clock frequency (rate)?
1ns = Clock Period (in ns) x Clock frequency (in GHz)
What is an equation describing the CPU Time in relation to Instruction Count, CPI, and Clock Frequency?
Many answers.
CPU Time = Instruction Count x CPI x Clock Period
CPU Time = Instruction Count x CPI / Clock Frequency/Rate
CPU Time = Instruction Count / Program x Cycles / Instruction (CPI) x Seconds / Cycle
DEFINE: CPI
Cycles per Instruction. The average number of cycles run for a single instruction.
DEFINE: RISC
Reduced Instruction Set Composition. A type of ISA that limits its number and complexity of instructions in order to increase clock rate.
DEFINE: CISC
Complex Instruction Set Composition. A type of ISA that uses many complex, powerful instructions to alleviate a slightly slower clock rate.
TRUE/FALSE: RISC uses fixed-width encoding, CISC uses variable-width.
TRUE.
What’s an example of a RISC ISA (outside of RISC-V)?
ARM (Advanced RISC Machines).
What’s an example of a CISC ISA?
Intel x86.
What are the two hallmarks of RISC ISA’s?
Fixed-width encoding and keeping memory and computational instructions separate.
Why are CISC systems able to compete with RISC despite RISC winning the race as it stands?
CISC processors now use RISC internals, and translate on the fly from the complex instructions to many simple ones.
What does the following RISC-V assembly do?
add x5 x6 x7
It adds x6 and x7 (register values) and stores the result in x5
Which of the following won’t you see in RISC-V (or really any RISC) ISA’s?
A) Instructions that use registers to commit to other registers
B) Instructions that combine register values and immediates to compute
C) Instructions that store the result of an operation in memory
D) Instructions that jump to other places in code
C. RISC is hallmarked on not mixing memory and computation.
DEFINE: Program counter
The special register that stores the memory address of the next instruction to be executed.
DEFINE: ALU
Arithmetic Logic Unit. Hardware that does computation.
Why are there no more than 32 registers in RISC-V (Think 256+, not 64)?
Encoding becomes more limited with more register id bits to contend with, and the computer has to read through the register file in each pass, which takes more time as the number of registers increase. It also simply takes up more silicon and power.
Why are there no less than 32 registers in RISC-V?
Less registers mean more spillover, where memory must be pulled from more often to access the same power level as 32 registers.
Notably, x86 has only 8 registers, so it’s not unthinkable to use less. ARM uses 16, for a RISC example.
TRUE/FALSE: Accessing memory is a significant bottleneck in performance.
TRUE.
TRUE/FALSE: When the Program Counter completes an instruction that doesn’t jump it, it moves forward by 1 byte in the RISC-V system.
FALSE. Since RISC-V has 32-bit encoding, it moves forward 4 bytes.
