The Hardware/Software Interface

Question 1

DEFINE: Abstraction

Answer 1

The use of simple calls to replace complex processes from the high-level developer or user.

Question 2

What are the three levels of the computer? What languages or processors do they utilize?

Answer 2

Applications software: Written in a high-level language (C, Python…)

System software: Assembly and machine code (binary)

Hardware: Not code, processors, memory, and I/O controllers

Question 3

DEFINE: ISA

Answer 3

Instruction Set Architecture. The abstraction between hardware and software.

Question 4

TRUE/FALSE: An ISA needs to be adjusted for every computer.

Answer 4

FALSE. As long as two computers have the same architecture, they can both run the same ISA.

Question 5

What are the three levels of program code? In RISC-V, what language do they use?

Answer 5

High-level language: C

Assembly language: Assembly for RISC-V

Hardware representation: Binary

Question 6

How many bytes do RISC-V instructions take up?

Answer 6

4 bytes (32 bits also OK)

Question 7

Even today, what is Intel’s biggest selling point in regards to its processors?

Answer 7

Backwards Compatability

Question 8

What three important criteria do we want to focus on when designing a “good” ISA?

Answer 8

High performance, power efficiency, and low cost

Question 9

Why can Apple design “more efficient” chips than Intel, ARM, or NVIDEA?

Answer 9

They design their chips for their own software, so they can focus on the areas they need.

Question 10

Against what is performance measured by?

Answer 10

Execution time (for a process, function, application, etc. Software).

Question 11

DEFINE: CPU Time

Answer 11

Time spent by the processor on a given job. Ignores anything else (such as I/O, other threads)

Question 12

What’s an equation that expresses the relation between clock period and clock frequency (rate)?

Answer 12

1ns = Clock Period (in ns) x Clock frequency (in GHz)

Question 13

What is an equation describing the CPU Time in relation to Instruction Count, CPI, and Clock Frequency?

Answer 13

Many answers.

CPU Time = Instruction Count x CPI x Clock Period

CPU Time = Instruction Count x CPI / Clock Frequency/Rate

CPU Time = Instruction Count / Program x Cycles / Instruction (CPI) x Seconds / Cycle

Question 14

DEFINE: CPI

Answer 14

Cycles per Instruction. The average number of cycles run for a single instruction.

Question 15

DEFINE: RISC

Answer 15

Reduced Instruction Set Composition. A type of ISA that limits its number and complexity of instructions in order to increase clock rate.

Question 16

DEFINE: CISC

Answer 16

Complex Instruction Set Composition. A type of ISA that uses many complex, powerful instructions to alleviate a slightly slower clock rate.

Question 17

TRUE/FALSE: RISC uses fixed-width encoding, CISC uses variable-width.

Answer 17

TRUE.

Question 18

What’s an example of a RISC ISA (outside of RISC-V)?

Answer 18

ARM (Advanced RISC Machines).

Question 19

What’s an example of a CISC ISA?

Answer 19

Intel x86.

Question 20

What are the two hallmarks of RISC ISA’s?

Answer 20

Fixed-width encoding and keeping memory and computational instructions separate.

Question 21

Why are CISC systems able to compete with RISC despite RISC winning the race as it stands?

Answer 21

CISC processors now use RISC internals, and translate on the fly from the complex instructions to many simple ones.

Question 22

What does the following RISC-V assembly do?

add x5 x6 x7

Answer 22

It adds x6 and x7 (register values) and stores the result in x5

Question 23

Which of the following won’t you see in RISC-V (or really any RISC) ISA’s?

A) Instructions that use registers to commit to other registers
B) Instructions that combine register values and immediates to compute
C) Instructions that store the result of an operation in memory
D) Instructions that jump to other places in code

Answer 23

C. RISC is hallmarked on not mixing memory and computation.

Question 24

DEFINE: Program counter

Answer 24

The special register that stores the memory address of the next instruction to be executed.

Question 25

DEFINE: ALU

Answer 25

Arithmetic Logic Unit. Hardware that does computation.

Question 26

Why are there no more than 32 registers in RISC-V (Think 256+, not 64)?

Answer 26

Encoding becomes more limited with more register id bits to contend with, and the computer has to read through the register file in each pass, which takes more time as the number of registers increase. It also simply takes up more silicon and power.

Question 27

Why are there no less than 32 registers in RISC-V?

Answer 27

Less registers mean more spillover, where memory must be pulled from more often to access the same power level as 32 registers. Notably, x86 has only 8 registers, so it's not unthinkable to use less. ARM uses 16, for a RISC example.

Question 28

TRUE/FALSE: Accessing memory is a significant bottleneck in performance.

Answer 28

TRUE.

Question 29

TRUE/FALSE: When the Program Counter completes an instruction that doesn't jump it, it moves forward by 1 byte in the RISC-V system.

Answer 29

FALSE. Since RISC-V has 32-bit encoding, it moves forward 4 bytes.