Circuit Design and Processor Design Constraints Flashcards
Complex ISA’s can slow down the _____.
Clock.
What prevents electric signals from being read as partial values (i.e. a strong signal as 2x the value of a weak one)?
Noise in the real world. Too much air radiation, inconsistency.
TRUE/FALSE: When sending or receiving a signal, a nullspace is added in the middle spots to prevent bit-flipping.
TRUE.
TRUE/FALSE: When we send a signal, we use a lesser nullspace than when we receive one.
FALSE. We use a greater nullspace, since when we send a signal, noise can push it closer to the other bit.
DEFINE: Buffer
A buffer is a component that cleans up signals in longer circuit wiring. It receives a somewhat dirty signal, then sends a clean one to prevent bit-flipping.
What is the level of abstraction above transistors?
The Standard Cell Library, which is a collection of pre-defined digital logic components to handle logic in the hardware.
What are the four major restraints in processor design?
Chip area, attainable clock speed, instruction-level parallelism, and Amdahl’s Law.
DEFINE: The chip area constraint.
The constraint that encapsulates chip size and manufacturing concerns. When chips get smaller, we need to concern ourselves with how fast they can go, and when chips get larger, we need to consider manufacturing defects caused by gravity or radiation. We get diminishing returns past a certain point.
DEFINE: The clock speed constraint.
The constraint that encapsulates additive delay.
DEFINE: The instruction-level parallelism constraint.
The constraint that increasing the number of ALU’s running at the same time stops scaling performance after a while.
DEFINE: The Amdahl’s Law constraint.
The constraint that certain instructions in a program are not parallelizable.
What are the two types of circuits? What does each do?
Combinational Circuits and Sequential Circuits. Combinational Circuits don’t work with memory or state, whereas Sequential Circuits do.
What’s the common microarchitectural component used to speed up combinational circuits?
Multiplexers (and demultiplexers).
DEFINE: Propagation delay.
The upper bound on the delay between an input signal to an output signal.
DEFINE: Additive delay.
The total of all circuit delays.
DEFINE: Contamination delay.
The lower bound on the delay from any input to any output.
DEFINE: Critical path.
The longest path from input to output (time-wise) in a given circuit.
How are sequential circuits made synchronous?
Through a clock mechanism that sends clock signals.
DEFINE: Setup time.
The time needed for the input to be recognized before the clock cycle hits.
DEFINE: Hold time.
The time needed for the input to be stable during which an operation is performed.
TRUE/FALSE: As long as propagation and contamination delay together are less than a clock cycle, the constraints are met.
FALSE. You must also ensure the Setup and Hold times are correct.
TRUE/FALSE: It’s often trivial to meet Setup time requirements, but difficult to meet Hold time ones.
FALSE. The opposite is true.
How are delays checked in circuit design (i.e. by which method)?
CAD tools.
What’s the major rule of thumb for making sure combinational circuits meet timing requirements?
One combinational circuit shouldn’t have to access too many pieces of state, and one piece of state shouldn’t be accessed by too many combinational circuits.
DEFINE: Timing Closure.
The meeting of timing constraints.
TRUE/FALSE: As the number of registers increases, the propagation delay increases. (Why?)
TRUE.
Multiplexers and demultiplexers must access more registers, which increases complexity, and often slows down the critical path.
TRUE/FALSE: Instruction-Level Parallelism focuses on parallelism within a single thread.
TRUE.
How does ILP parallelize?
Through hardware, using different ALU’s and components simultaneously.
TRUE/FALSE: Amdahl’s Law speeds up individual processes by utilizing multicores.
FALSE. Amdahl’s Law focuses on running different threads, leaving the speed of individual ones the same.
What is the equation for Amdahl’s Law?
Speedup = 1 / ((ProportionOfParallelizableFunctions / n) + (1 - ProportionOfParallelizableFunctions))
